whitequark[cis] changed the topic of #prjunnamed to: FPGA toolchain project · rule #0 of prjunnamed: no one should ever burn out building software · https://prjunnamed.org · https://github.com/prjunnamed/prjunnamed · logs: https://libera.irclog.whitequark.org/prjunnamed
gatecat[m] has joined #prjunnamed
<gatecat[m]> <whitequark[cis]> "the right boundary is something..." <- huh, I thought keep_hierarchy was actually taken from Vivado
<whitequark[cis]> i think that is true but in practice what i have seen used is (a) block design stuff which automatically does EDIF hacks (or some other netlist format?) and (b) manually set up EDIF hacks
<whitequark[cis]> like in an actual ASIC product environment
<whitequark[cis]> this is because people want to share synthesis results between runs and sometimes between people by checking it in
<whitequark[cis]> keep_hierarchy does not let you do that
<whitequark[cis]> if it's big enough for the added time to matter it's big enough that caching it will be even better
<whitequark[cis]> povik (Martin Povišer): now that you have one PR in, you can get a commit bit if you want, per our policy
<povikMartinPovie> Thanks, it might become useful later if I contribute something more substantial
<povikMartinPovie> If you have branch protection then I don’t see a downside
<whitequark[cis]> added you to the ACL
<whitequark[cis]> actually, just re-added you to the ACL in a different way (so that it is a "team", not individual loose collaborators which will get unwieldy quickly)
<whitequark[cis]> mei: also moved you to the team, you might get an email notification about this
<whitequark[cis]> also fixed up access to ancillary repos