<mei[m]>
btw why the distinction between TestTarget and MockTarget?
<whitequark[cis]>
they're just local to their respective unit test modules
<whitequark[cis]>
i think i wrote one and Wanda wrote another
<mei[m]>
completely unrelated: do you enforce any restrictions like "there must be no combinatorial cycles" during import?
<mei[m]>
i see that there's Cell::validate but that seems like more local stuff
<mei[m]>
also, what's the difference between Cell::Name and Cell::Output?
<Wanda[cis]>
<mei[m]> "completely unrelated: do you..." <- we don;t; we should
<Wanda[cis]>
we're also going to need it to e nforce target-specific rules
<mei[m]>
i wonder if there's any nice datastructures that would let you verify that the invariant is being maintained during optimizations 🤔
<Wanda[cis]>
like "carry in pin must be connected to carry out pin, with no branches"
<Wanda[cis]>
<mei[m]> "also, what's the difference..." <- as for that... long story
<Wanda[cis]>
it's kind of debugging-related
<Wanda[cis]>
output is "this is actual output of the circuit, make it an IOB unless doing out-of-context mode"
<Wanda[cis]>
name means you just want to poke at it with debugger
<Wanda[cis]>
name will likely be redesigned several times.
<Wanda[cis]>
as we figure out what it should mean
<Wanda[cis]>
in particular, name cell has strong semantics: it keeps the value alive; we'll also need some way to represent best-effort debug names which get unalived when the value is otherwise unused
<leocassarani[m]>
So as things stand right now, if someone is writing IR intended for synthesis they shouldn't use name, but if they're wanting to run a simulation they can add all the necessary name cells so that certain nets don't get optimised away?
<leocassarani[m]>
* So as things stand right now, if someone is writing IR intended for synthesis they shouldn't use name (to avoid a performance hit), but if they're wanting to run a simulation they can add all the necessary name cells so that certain nets don't get optimised away?
<whitequark[cis]>
we remove all `name` cells in the synthesis flow
<whitequark[cis]>
you shouldn't need to explicitly care about it
<leocassarani[m]>
oh I think I've misunderstood the idea of a name cell keeping a value alive
<whitequark[cis]>
I think you have it right
<mei[m]>
so, what's the point of having the Buf cell?
<whitequark[cis]>
you can replace something else with it
<mei[m]>
...like Void?
<Wanda[cis]>
mei[m]: kind of "you need stuff like this in corner cases when you're building a netlist, and when you do, better this than `or a 0`"
<Wanda[cis]>
JSON importer uses it, I think?
<Wanda[cis]>
for importing yosys buffer cells
<whitequark[cis]>
also the lower pass
<whitequark[cis]>
it's incredibly cheap to support so there isn't really a reason not to
<Wanda[cis]>
oh, yosys import actually doesn't use it
<Wanda[cis]>
apparently the RAUW chains just work out
<whitequark[cis]>
yeah it must be just the lower pass and also some tests
<Wanda[cis]>
lower... I think I wanted to return a cell at some point, instead of a value, so I used a buffer?
<Wanda[cis]>
this was before we had void cells, so maybe it should be done differently now
<mei[m]>
the docs claim that adc_split turns { a b 0 0 } + { 0 0 c d } into a buffer
<Wanda[cis]>
... the what?
<Wanda[cis]>
oh that.
<Wanda[cis]>
yeahhh, I kinda use "a buffer" synonymously with RAUW
<Wanda[cis]>
may be yosys brain damage
<mei[m]>
RAUW?
<mei[m]>
that kinda sounds like a sound a furry would make
<mei[m]>
(i have no idea what it actually means, please do explain)
<Wanda[cis]>
and yes, the implementation of adc_split is comically short compared to what it does, and compared to the comment describing wtf it does and why it's useful; I very much like it that way
<Wanda[cis]>
in fact, removing start_offset will make it even more comically short, so I like that idea
<Wanda[cis]>
mei: so have you looked at `adc_unsext` yet
<_whitenotifier-4>
[prjunnamed/prjunnamed] meithecatte 184ab85 - Remove invalid implementation of Cell::slice for match cells
* mei[m]
looks at adc_unsext
<mei[m]>
ah, this must be the optimization that got subposted on fedi
<Wanda[cis]>
oh ye
<Wanda[cis]>
* oh yes
<Wanda[cis]>
I mean, so was adc_split
<mei[m]>
i feel like the simplifier, as currently written, will need to be run twice if both the adc_split and adc_unsext cases occur within one cell
<Wanda[cis]>
<mei[m]> "one case it doesn't seem to be..." <- okay, so about that one
<Wanda[cis]>
I actually don't think this should be done, except at the top bits
<Wanda[cis]>
this is due to the way carry chains work on FPGAs
<Wanda[cis]>
the optimization, as stated, requires grabbing an intermediate cout and putting it out on the fabric
<Wanda[cis]>
which cannot be done on eg. ice40, at least not without inserting an intermediate SB_CARRY on the chain at the place where you want to extract the carry
<Wanda[cis]>
in fact, the optimization isn't expressible in our IR either — the adc cell doesn't give you the intermediate carry outs. and this is a design decision that is motivated by exactly this property of carry chains.
<Wanda[cis]>
(the intermediate SB_CARRY you'd have to insert is, in fact, exactly equivalent to the original 0 + 1 + ci bitslice)
<Wanda[cis]>
however. this varies with target. on Xilinx FPGAs, you can actually grab the intermediate carry-outs for ~free, so the optimization would be worthwhile.
<Wanda[cis]>
not sure how to proceed with this; might just go and recognize it within the Xilinx techmapper that lowers the adc to the carry chain?
<Wanda[cis]>
looks Lattice also has extra couts for free
<Wanda[cis]>
... while Altera does not
galibert[m] has quit [Quit: Idle timeout reached: 172800s]
<Wanda[cis]>
once again reinforcing the Xilinx/Altera gender binary huh.
<_whitenotifier-4>
[prjunnamed/prjunnamed] meithecatte ee57d0d - Remove needless clones in calls to replace_value
<_whitenotifier-4>
[prjunnamed/prjunnamed] meithecatte 2cd249b - iter::repeat_n(1) is just iter::once
<_whitenotifier-4>
[prjunnamed/prjunnamed] meithecatte 336dfb3 - pattern: Use $crate where possible
<_whitenotifier-4>
[prjunnamed/prjunnamed] ... and 3 more commits.
<whitequark[cis]>
<mei[m]> "no functional change" <- often referred to as "non functional change" when someone else cheerfully breaks your buildbot with an NFC commit
<whitequark[cis]>
this is considered a rite of passage.
<Wanda[cis]>
ohhhh the LLVM buildbots
<whitequark[cis]>
oh, we should set up a merge queue at some point
<Wanda[cis]>
good times
<Wanda[cis]>
oh yes
<whitequark[cis]>
Wanda[cis]: they still exist!
<Wanda[cis]>
yea I just haven't touched LLVM in ages
<mei[m]>
whitequark[cis]: i think github has a builtin one these days?
<Wanda[cis]>
yeah that's what we meant
<Wanda[cis]>
it's used with .... reasonably good results on amaranth and glasgow
<mei[m]>
also, we should set up benchmarks like "time to synthesize $project", "luts used to synthesize $project", and have a graph that shows how it changes with each commit
<Wanda[cis]>
would be great results, if not for checks notes multidict, gnu.org, and ubuntu
<Wanda[cis]>
mei[m]: ... we should start with actually collecting testcases
<whitequark[cis]>
Wanda[cis]: agreed
<Wanda[cis]>
like. actual real projects hooked up to ingest them to unnamed.
<whitequark[cis]>
pretty charts are cool but we need the data first
<mei[m]>
well you have boneless and minerva so far...
<Wanda[cis]>
ac97_ctrl
<whitequark[cis]>
mei[m]: yes but it will prevent me from force pushing to main (to keep everyone on their toes)
<whitequark[cis]>
Wanda[cis]: aaaaaaaaa
* Wanda[cis]
prepares to get hissed at
<whitequark[cis]>
i mean yeah sure.
<mei[m]>
Wanda[cis]: fill me in?
<Wanda[cis]>
so uh.
<Wanda[cis]>
read a logic optimization paper. any paper.
<whitequark[cis]>
<del>phrasing
<mei[m]>
whitequark[cis]: sounds like a bdsm dynamic
<Wanda[cis]>
they invariably have the sameish set of benchmarks
<whitequark[cis]>
mei[m]: Wanda said i should be doing it and i obliged
<Wanda[cis]>
which includes... some random simple circuits literally copy-pasted 100× times or some shit like that
<whitequark[cis]>
well i also wanted to, because of the ocd
<Wanda[cis]>
and then they boast about how well the new algorithm optimizes it to something small
<whitequark[cis]>
Wanda[cis]: and ac97!
<mei[m]>
Wanda[cis]: "look ma, functional GVN!!"
<Wanda[cis]>
for inscrutable reasons, the list also includes ac97_ctrl
<whitequark[cis]>
i nominate Hazard3 for the benchmarks
<whitequark[cis]>
we should try to synthesize that in fact
<whitequark[cis]>
mei, you up?
<Wanda[cis]>
I mean
<mei[m]>
oops, all softcores
<whitequark[cis]>
lol
<Wanda[cis]>
I believe we should go the shovelware way here
<mei[m]>
whitequark[cis]: hooking shit up as input? no idea how that works tbqh
<whitequark[cis]>
shove it into yosys
<Wanda[cis]>
as long as it's actual circuits someone uses, and not fucking copy-paste
<whitequark[cis]>
cause verilog
<whitequark[cis]>
Wanda[cis]: yes but build systems...
<mei[m]>
would you believe me if i told you i never used yosys?
<Wanda[cis]>
you did!
<mei[m]>
outside of maybe amaranth handling it all for me
<Wanda[cis]>
well. amaranth did.
<whitequark[cis]>
mei[m]: oh, happy woman (?)
<mei[m]>
which doesn't count for "knowing how to use it"
<Wanda[cis]>
hmmm
<whitequark[cis]>
god. i wish i never used yosys
<Wanda[cis]>
mei what is your gender
<mei[m]>
whitequark[cis]: please. girlthing if anything. read the room. /lh
<Wanda[cis]>
(glad to be asking this question while out of biting range this time)
<Wanda[cis]>
we could make you more unhappy if you want
<whitequark[cis]>
we could!
<mei[m]>
uhhhhhh
<mei[m]>
by way of verilog fun facts?
<whitequark[cis]>
this project is such good masochism value for time
<Wanda[cis]>
by way of interacting with yosys, this time
<whitequark[cis]>
mei[m]: also yosys fun facts
<whitequark[cis]>
also vendor fun facts
<whitequark[cis]>
o:3
<mei[m]>
so, would our benchmarks go to the examples/ directory?
<mei[m]>
i was surprised not to find boneless nor minerva there
<Wanda[cis]>
I'd think they'd go to a separate repo?
<Wanda[cis]>
like, if it's any good, it's going to include a bunch of heavy shit you don't want to clone together with unnamed if you just want the toolchain