whitequark[cis] changed the topic of #prjunnamed to: FPGA toolchain project · rule #0 of prjunnamed: no one should ever burn out building software · https://prjunnamed.org · https://github.com/prjunnamed/prjunnamed · logs: https://libera.irclog.whitequark.org/prjunnamed
<vancz> whats the point of sensitivity lists if youre just going to pattern match on an "if", to match the reset signal during synthesis anyway :/
<vancz> ah wait i think i might be being snarky about something im not understanding
<vancz> i guess for synchronous reset you _are_ on the clock so it makes sense that the clock is the only thing in the sensitivity list, nevermind
<whitequark[cis]> sync reset (as well as enable) is not anything special and the synthesizer will often find signals not "intended" as reset or enable but use them as such
<whitequark[cis]> this is not syntactic though, those may come from an entirely other module