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<_whitenotifier-4> [prjcombine] wanda-phi opened issue #8: Design a means of obtainint and storing bel "prototypes" and passing them to prjunnamed - https://github.com/prjunnamed/prjcombine/issues/8
<_whitenotifier-4> [prjcombine] wanda-phi edited issue #8: Design a means of obtaining and storing bel "prototypes" and passing them to prjunnamed - https://github.com/prjunnamed/prjcombine/issues/8
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<Wanda[cis]> mmm
<Wanda[cis]> seems Digilent made quite a few boards with FX2 + FPGA (Nexys 1/2/3, Genesys, Atlys, Basys rev E, ...)
<Wanda[cis]> and they all have the proper FX2 connections for FIFO and JTAG
<Wanda[cis]> I wonder how hard it would be, when the time comes, to run the glasgow stack on them
<_whitenotifier-4> [prjcombine] wanda-phi opened issue #9: Get rid of the argument to `WireKind::ClkOut` - https://github.com/prjunnamed/prjcombine/issues/9
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