<azonenberg>
Wanda[cis]: almost every time i think i know how the GTY works it's proven me wrong
<azonenberg>
The parameter vexing me right now is PREIQ_FREQ_BST
<azonenberg>
it follows a *rough* pattern: starting out at 0 for really low data rates, then 1, then 2 at 20 Gbps, 3 at 25 Gbps (these are not exact cutoffs just data points I have)
<azonenberg>
But it's not monotonic
<azonenberg>
I have a 7 Gbps config where it's 1, then 10 and 10.3125 where it's back to 0, then 1 at 15 Gbps
<azonenberg>
I thought i had it figured out, then started making more configs to fill in the gaps and find the exact transition point and i find it's not monotonic
<azonenberg>
so now i'm confused and wondering if there's another variable i'm not understanding that impacts it somehow
<mupuf>
azonenberg: or it doesn't matter much, but I guess better be safe and replicate the algorithm
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<azonenberg>
mupuf: I want to understand the algorithm first
<azonenberg>
I'm on the road now but when i'm back at my desk i can start doing controlled experiments where i actually measure BER and eye pattern shape etc with various parameters
<azonenberg>
and see if i can observe a change in the ones i'm unsure of
<mupuf>
azonenberg: the perks of having well equiped lab like yours
<azonenberg>
Lol yep
<azonenberg>
The overlap between people doing FPGA RE and people with the equipment to properly study high speed SERDES waveforms is... quite possibly just me lol
<azonenberg>
both are fairly small groups and the vast majority of folks with scopes this nice are working on the design side
<mupuf>
You and vendors looking at their competitors' product... maybe
<azonenberg>
Competitive analysis people probably only care about specs
<azonenberg>
not every nitpicky detail of every config knob
<azonenberg>
It's either "is mine better? if so, by how much? if mine falls short, where?" or "are they infringing on my patent?"
<azonenberg>
in the latter case, RE is going to be narrowly scoped to what it takes to prove infringement
<azonenberg>
rather than the sorts of stuff we do here, where we want *everything*
<azonenberg>
at least on the bitstream/config side, we dont really care about whats going on at the circuit level except as a clue to how the bitstream works
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