<Wanda[cis]>
(this is what happens when you leave me unattended with a devboard with a funny programmer)
<Wanda[cis]>
(the protocol has way more features than that, but I only bothered to document the stuff supported in the two boards that I currently have on paw)
<Wanda[cis]>
(also I believe most other boards involve an FX2, which makes supporting them in open-source tooling a significantly more complex undertaking)
<mupuf>
prjcombine: the "reverse the world" project of Wanda :D
<Wanda[cis]>
it's used to put bitstreams into FPGAs. it's relevant.
<mupuf>
indeed, still was fun to see
<azonenberg>
Wanda[cis]: lol
<azonenberg>
any chance i could convince you to RE another fpga-adjacent protocol?
<azonenberg>
(the vivado debug hub / ILA / VIO)
<azonenberg>
i.e. i want to be able to use ngscopeclient to pull waveforms off ila ips
<Wanda[cis]>
I don't consider that to be useful for my purposes
<azonenberg>
Fair enough
<azonenberg>
it's been on my wishlist for a while just because of how nicely the vivado cores integrate with the synthesis flow so i dont have to manually wire up jtag to each target
<Wanda[cis]>
ultimately, that's just some particular gateware that vivado puts on the FPGA; the underlying hardware mechanisms are interesting to me, but I believe they are quite far removed from what you want, and probably all already known
<azonenberg>
yes its just the BSCANE2
<Wanda[cis]>
yeah figured
<azonenberg>
What's not known is the protocol running over the USER1...4 registers
<azonenberg>
Which is important for interop with third party tools
<Wanda[cis]>
yeah.
<Wanda[cis]>
and that's the kind of thing I'd be more interested in replacing than reversing
<azonenberg>
right now there's no way to get a waveform out of an ILA without using tcl to script vivado and then writing it out to a vcd file
<azonenberg>
Yeah i plan to replace it too but that doesnt mean i dont also want to be able to interop with third party rtl using it
<azonenberg>
also related: what would be cool in prjunnamed eventually is the ability to do automatic late-in-design debug IP insertion
<azonenberg>
in other words, i have some kind of script with a bunch of hierarchical net paths
<azonenberg>
and it'll wire them up to a logic analyzer core no matter where in hierarchy they are
<azonenberg>
and ideally then have the same insertion pass insert any other jtag modules needed to make the (potentially multiple) logic analyzer cores all interop with each other and share one BSCAN block
<azonenberg>
basically i dont want to have to modify my rtl to add debug cores, i want to be able to do it as an out-of-tree thing in a synthesis script or something
<Wanda[cis]>
there are some long-term plans like that, yeah
<azonenberg>
I have some ideas on a suite of open source debug cores that will replace the vivado ones, probably using my existing APB infrastructure blocks for talking among themselves
<azonenberg>
in order to avoid the risk of stalling the fabric with a bug in the user's design, this will be a completely parallel APB interconnect that's independent of any APB that might be used in the user design
<azonenberg>
that only connects debug IPs, with a root in the BSCAN-to-APB bridge i have yet to build
<azonenberg>
like, i could do this today with a bit of engineering work, it'll just require extensive rtl modifications to add an apb port to each level of hierarchy that i want debug cores in
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