klange changed the topic of #osdev to: Operating System Development || Don't ask to ask---just ask! || For 3+ LoC, use a pastebin (for example https://gist.github.com/) || Stats + Old logs: http://osdev-logs.qzx.com New Logs: https://libera.irclog.whitequark.org/osdev || Visit https://wiki.osdev.org and https://forum.osdev.org || Books: https://wiki.osdev.org/Books
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<heat> operating s
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<linkdd> quick question, is IRQ1 specific to PS/2 keyboards, or is it triggered for USB keyboards as well?
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<zid> modern PCs are set up to fake it yes
<dminuoso> Wouldnt they realistically arrive as IRQ2 via a slaved PIC though?
<pitust> why would it?
<zid> IRQ2 chains to the 2nd pic
<zid> IRQ1 is on the first pic
<zid> so no, IRQ1 is IRQ2, it's IRQ 8-15 that are also an IRQ2
<zid> IRQ1 is IRQ1*
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<linkdd> zid: from your screenshot, i understand that if bios is selected i receive an IRQ1, and if OS is selected i don't?
<zid> yea
<pitust> if BIOS is selected, SMM will pretend to you that there is a ps/2 keyboard attached
<linkdd> if OS is selected then my usb driver should do the work?
<zid> It's emulated using stuff called SMM/SMI
<pitust> else, you need [OUX]?HCI and stuff
<linkdd> also, are IRQ x86 specific?
<zid> No, but how they're delivered and how they're processed is
<linkdd> so the IDT is x86 specific, but not the IRQ
<zid> Gameboy for example has 5 IRQs total, masked individually via a register at 0xFFFF, acknowledged via a bit in 0xFF0F, and eah cause an interrupt to run at address 0x40, 0x48, 0x50, 0x58 and 0x60 respectively
<zid> and each are just connected to an external pin on the IC package, rather than using the little protocol the 8259 does
<mrvn> ARM has just 2
<mrvn> and also many many
<zid> some chips have no external interrupt sources at all
<zid> For those instead you would just check your devices in your `main loop` as it were, if you had any
<pitust> arm is funny, because while there are two, linux on !apple uses just one
<zid> x86 has about 8000 irq delivery mechanisms I think
<zid> arm isn't even trying
<linkdd> ok thank you for all the information :)
<pitust> x86 has PIC, LAPIC+APIC, MSI and MSI-x
<pitust> arm has MSI+MSI-X, and then also AIC1, AIC2 (apple), GIC, some older primecell, VCIC
<pitust> two pins though, FIQ and IRQ
<j`ey> (and different version of the GIV)
<j`ey> *GIC
<pitust> and linux on !apple panic(s|ed) on FIQs
<j`ey> VCIC == VGIC?
<pitust> VideoCore interrupt controller
<j`ey> oh, rpi
<pitust> yeah
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<Bitweasil> zid, j`ey, that's true of A series ARM, the M series cores have an x86-like vectored interrupt controller that's an awful lot nicer to use from everyone I've talked to.
<Bitweasil> IIRC 256 distinct vectors.
<Bitweasil> I'm not sure why someone hasn't bolted that to an A-series core concept.
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<mrvn> Bitweasil: because in many cases the kernel just load the interrupt number into a register or dump it on the stack and call common code.
<Bitweasil> Sure, it's just more cycles than having that as part of your interrupt calling.
<mrvn> I mean in the case of having an interrupt vector.
<mrvn> I think what makes the M series nicer is that the interrupts use C calling conventions. Not that you have 256 of them.
<Maja[m]> mrvn: "Would a core fetch from the write back buffer of another core?" it won't according to https://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf
<geist> Bitweasil: yeah that's correct. the M series has a pretty powerful vectored interrupt controller. NVIC
<geist> i think it can go past 256 though. what it has is up to 256 priority levels, though in my experience most vendors only implement 8 or 16 of them (it's an option in the RTL)
<Bitweasil> Yeah, I've not had to implement it, but I've read the docs on it and it looks fancy!
<Bitweasil> It's still far more flexible than the stuff typically on the A series.
<Bitweasil> I was faintly surprised Apple didn't change that around with their silicon.
<Bitweasil> Would have been easy enough to put a good interrupt controller on, I guess it just doesn't matter that much for their use cases.
<geist> yeah the apple intc is pretty weird
<geist> or more specifically, seems to be following on from the armv6 days, when IRQ and FIQ were actually used as two vectors
<geist> vs what ARM usually does with them now and effectively reduces them to insecure and secure vectors, respectively
<Bitweasil> Right, I think I saw they were actually using FIQ as more or less intended.
<Bitweasil> Right.
<geist> since apple doesn't use the secure mode stuff it makes sense they kept it the other way
<mrvn> Isn't it kind of pointless in bigger CPUs? The few opcodes to pick an interrupt are trivial and the amount of work you do in an interrupt handler has gotten bigger over time.
<geist> though GIC would also let you use IRQ/FIQ generically if you configured it as such
<geist> you can nest them, so if you want a very very low latency thing you can toss it on FIQ
<geist> but yes, usually doesn't need to exist in modern designs
<Bitweasil> Do you still have register banking with FIQ on AArch64?
<geist> no
<Bitweasil> Ok.
<mrvn> urgs, that's the whole point of FIQ
<geist> in arm64 it's functionally just a separate exception vector + disable bit
<geist> with an implicit higher priority than irq
<geist> but yes, for most practical purposes in most designs (aside from apple) it's used as a separate irq line that the EL3 code sets a control bit to redirect to itself
<mrvn> The part that makes the FIQ fast is the banked register saving time by not having to save state.
<geist> note that ARM didn't really invent that, i think it was kinda in the air. 6809 had a FIQ mode, more or less thes ame as IRQ
<geist> i think some of the other motorola chips at the time had something like that, though double checking, looks like 6800 just had IRQ
<geist> and of course 68k had a much more complicated scheme than two levels
<mrvn> m68k has levels but no register banking.
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<mrvn> Back then you wanted nested interrupts.
<mrvn> (by priority)
<geist> looking at FIQ on 6809, it was similar, but not the same scheme
<geist> basicall it's a separate vector, but the cpu itself saves less state: IRQ saves the full cpu state automatically on the sack, FIQ only saves PC + flags
<mrvn> so kind of the opposite implementation
<geist> but yeah, what also makes FIQ less useful on arm64 is *all* exceptions + interrupts also mask the I and F bits in the PSTATE register. so you have to manually re-enable fiqs
<geist> so you can't even automatically interrupt an interrupt like you can on arm32
<mrvn> You save what you need, we don't save anything we don't have to
<mrvn> geist: that's odd. I would have though irq disabled I and FIQ disabled both. That would be priorities.
<geist> same. but there are reentrancy reasons why so. since there is no banking, it wouldn't really be safe for the cpu to interrupt another one
<mrvn> Does arm64 still have an IRQ and FIQ stack?
<geist> you have to have at least a few instructions to save away critical satate
<geist> no
<geist> there's no banking, period.
<mrvn> there is your reason then
<geist> exactly
<geist> all of the banking in arm64 is per EL level. so again the main reason FIQ still exists on arm64 is for 32bit compatibility, and to treat it as secure vs insecure
<geist> note that at least all of the early (ie, first 10 years) of armv8 machines can also run natively in 32bit mode so it still has banking, it justonly works when in 32bit mode. ie, all the 32bit supervisor machinery is still there, and thus IRQ and FIQ hardware has to still exist
<mrvn> I guess if a 32bit kernel sets up and FIQ then you want the hypervisor to handle that throught the FIQ handler too
<geist> right
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<mrvn> don't want to block the FIQ while inside the IRQ handler.
<geist> you really should do some 64bit hackery
<geist> as much as you're an arm fan, you are still mostly doing arm32 iirc
<geist> or at least judging by your questinos about arm64
<mrvn> yeah, haven't gotten past jumping to higher half on arm64 yet.
<geist> well, ifyo uever need any help a few of us have made it past the jump
<geist> and the grass is green and the air is fresh over here
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<Bitweasil> Seriously, AArch64 gets rid of a ton of the cruft that built up by late ARMv7.
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<mrvn> They rebootet Quantum Leap. I guess it's Dinner and a Movie^WTV show tonight
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<moon-child> Griwes: partitioning branches 'not worth it', eh? :)
<Griwes> I, uhhh, have no context for this message
<bslsk05> ​libera.irclog.whitequark.org: #osdev on 2022-06-28 — irc logs at libera.irclog.whitequark.org
<bslsk05> ​developer.nvidia.com: NVAPI - Get Started | NVIDIA
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