NishanthMenon changed the topic of #openocd to: this is the place to discuss all things OpenOCD | Logs: https://libera.irclog.whitequark.org/openocd/
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<eliasph88> Hi all, I am trying to use OpenOCD with a Xilinx Alveo U280 board (been here last week in fact). Trying to understand a couple of stuff.
<eliasph88> 1. OpenOCD documentation (page 16) explains when using configuration files for interface, board and target. But,in which scenario do I use cpld configuration files.
<eliasph88> 2. In the ../openocd/tcl/target/xilinx_zynqmp.cfg is there any way to obtain support for the alveo u280?
<eliasph88> 3. In the ../openocd/tcl/cpld/xilinx-xcu.cfg there is a list of Xilinx devices up to the alveo u250, is there any updates thinking on the Alveo u280 or U55C?
<eliasph88> Thanks in advance
<PaulFertser> Hi, welcome back.
<PaulFertser> I'm not sure you really need support for a specific CPLD.
<PaulFertser> Or FPGA
<PaulFertser> eliasph88: because if you want to just load bitstream to the target FPGA you can ask the IDE to generate an SVF file and then just play back the SVF file with OpenOCD. For that you just need an interface config basically.
<PaulFertser> eliasph88: to answer your first question properly, the CPLD configuration files are for PLD target devices, so they're kind of a target config.
<PaulFertser> For the second question, I have no idea. What exactly is missing, which feature is not supported or different on that board?
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<eliasph88> Thanks Paul, agree with no need to loadbitstream from here (so CPLD configs are not my solution) in my case I would need a config file like the ones in the target folder target which integrate CPUs and other JTAG TAPs then
<PaulFertser> eliasph88: as to the third question, you can read the source code in src/pld/virtex2.c and compare with the procedure described by datasheet/appnote/refman for your part to see if it's applicable. If yes, just add an ID to the list.
<PaulFertser> eliasph88: if you only need on-chip-debug (breakpoints etc) of the CPU core then you do not need to care about any PLD files.
<eliasph88> The alveos U280 and U55d are ones which included the HBM but nothing more interesting in other sense as far as I know
<eliasph88> great thats exactly what I did
<eliasph88> added a line for these board which in fact have the "same" fpga
<eliasph88> thanks
<eliasph88> whill take a look to your reply to my third question then
<PaulFertser> eliasph88: I still have zero idea about what exactly you want to do with that board...
<eliasph88> XCU280_U55C {0x14b7D093 18} #just one line ;)
<eliasph88> I´m sorry I thought I have explained
<eliasph88> Something like this you shared
<eliasph88> is just a different SoC; RISC-V and board
<PaulFertser> Hm, so you're not using the Zynq ARM hardcore, you have that FPGA run some RISCV softcore instead and you want OCD access to it?
<PaulFertser> Or what?
<eliasph88> exactly, in fact I can be more transparent because is open hw
<PaulFertser> So is it a soft core? Then what did the softcore authors tell you exactly about what they did for debug there?
<eliasph88> my SoC is OpenPiton, mi board is the alveo u280/u55c and the RISC-V is of our own development
<eliasph88> and what we want to do is to access the JTAG TAP inside our chip whish is a soft core inside our FPGA
<PaulFertser> OpenPiton seems to be another core, totally unrelated.
<eliasph88> they were able to debug it on simulation with remote-bitbang
<PaulFertser> SPARC-based. And available both as soft core and as ASIC RTL.
<eliasph88> yes indeed, but we use the framework and NoCs but replace their standard core by ours
<PaulFertser> OK, so.
<PaulFertser> Your HDL engineers are supposed to tell you all the details about how they hooked up the debug.
<PaulFertser> Right?
<eliasph88> right
<eliasph88> is exactly like in the link with a BSCAN2JTAG
<PaulFertser> eliasph88: also, do not you have few spare pins available there? Can't you ask them to temporarily route it to a dedicated JTAG port?
<eliasph88> which works with in simulation with this (i think is small enouhg)
<eliasph88> "/src/openocd -c "debug_level 4" -c "adapter driver remote_bitbang" -c "remote_bitbang host localhost" -c "remote_bitbang port 44853" -c "jtag newtap op unknown0 -irlen 18 -expected-id 0x01aaa07d" -c "target create op openpiton -chain-position op.unknown0" -c "init"   "
<eliasph88> yes the pin solution I am also exploring it, the board has a FTDI4232HQ USB-JTAG and also been contacting AMD to get the constrains to route it directly as you say
<PaulFertser> It's pretty clear the simulation doesn't match your real thing or else this would just work with same "jtag newtap" and "target create" command and the adapter config sourced before that.
<PaulFertser> Also, this is not vanilla OpenOCD, there's no "openpiton" target present in the code.
<PaulFertser> eliasph88: what did your HDL people say after you showed them results of auto-detection, how do they explain the taps differ from the simulation?
<PaulFertser> eliasph88: in simulation you have just a single tap.
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<eliasph88> totally agree with you that is definitely not vanilla OpenOCD, not for me indeed :)
<PaulFertser> Vanilla here means "unmodified upstream"
<eliasph88> I finally have a meeting with them on Friday, definitely going to inquire them why 1 tap/2 tap
<PaulFertser> Heh
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<PaulFertser> That's just too weird, if you're doing the job together how come you can't just ask.
<eliasph88> Ohh i used it as vanilla = "not straightforward" heh
<PaulFertser> You ask me, I answer. And your team members are supposed to be even more helpful.
<eliasph88> not happy about it over here for sure
<PaulFertser> Not make you wait for weeks.
<PaulFertser> Especially during the bringup stage.
<eliasph88> Thanks Paul for your time. I will collect some more inside info before coming again
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<PaulFertser> If they did exactly what that BSCAN2JTAG links says then exact same approach to OpenOCD describe there on the page should work.
<PaulFertser> eliasph88: feel free to ask but here it's a serious project, a rather unusual target and there's nothing to guess here really. Or you should get the HDL code yourself, read it, understand how it's all coming together wrt debug and then you'd be able to give the answers yourself.
<eliasph88> thanks
<PaulFertser> eliasph88: btw, that FTDI4232H has not one but four (!) interfaces. So if at least one of them is connected to some FPGA signals you can just connect the softcore's JTAG there directly, right?
<PaulFertser> eliasph88: I assume you have schematics?
<PaulFertser> You only need the first 4 signals of an interface to do JTAG.
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