00:24 <phr3ak> what is ircapture 0x1?

14:31 <phr3ak> does it mean only the first LSB bit value will be checked?

14:42 <PaulFertser> phr3ak: yes, of the value it read during initial examination of IR.

14:43 <PaulFertser> IoTMaker: so you're comparing jlink commander using JTAG and OpenOCD using SWD? That's not a fair comparison.

14:49 <PaulFertser> IoTMaker: so you're comparing jlink commander using JTAG and OpenOCD using SWD? That's not a fair comparison.

14:50 <IoTMaker> PaulFertser no i don't compare jtag/swd. I used both with jtag. SWD was just a question. Don't know why this hint is in my logfile.

14:50 <PaulFertser> If yoou have "SWD DPIDR 0x5ba02477" in the log file then it's using SWD.

14:53 <Mis012[m]> PaulFertser: no, I was just asking if OpenOCD prints a textual description for the ID with JTAG but not with SWD

14:54 <Mis012[m]> since the log had a textual description, but my log with SWD doesn'T

14:55 <PaulFertser> Mis012[m]: over SWD you get only ARM, so there's nothing to describe really. Probably a small list of ARM core IDs can be added but it doesn't really help much, and later when the core is examined its full type is printed already.

14:57 <Mis012[m]> PaulFertser: well, from looking up the id online and seeing what different cores it's used on, it's probably not refering to a core type

14:58 <PaulFertser> Mis012[m]: 0x5ba02477 looks like Cortex-M7 or something like that.

14:58 <Mis012[m]> PaulFertser: yeah, but it's probably not

14:59 <PaulFertser> Mis012[m]: huh? how so?

14:59 <Mis012[m]> closest in the SoC is M3, but it's probably for the armv8 cores since I saw it in logs for kirin as well

15:00 <Mis012[m]> presumably it means something like CoreSight, possibly a specific IP revision

15:00 <PaulFertser> Mis012[m]: I know different Cortex-M variants have it different.

15:01 <PaulFertser> Mis012[m]: probably it's some DAP version actually.

15:01 <PaulFertser> Are you able to examine a core on any of the APs?

15:02 <Mis012[m]> I think I've identified the right IP from t32 scripts I have access to

15:02 <Mis012[m]> but examination fails

15:02 <Mis012[m]> is it possible that the boot core needs to be manually started after SRST?

15:03 <Mis012[m]> the t32 scripts contain code for that in a reset routine

15:03 <Mis012[m]> next up I think I'll just specify mem-ap as the target

15:03 <PaulFertser> Quite possibly so

15:04 <PaulFertser> Yes, if you can manipulate mmio via mem-ap you can possibly translate those t32 commands to OpenOCD language.

15:04 <Mis012[m]> well, it's just simple memory writes that I can probably understand and write a better explanation for :P

15:05 <Mis012[m]> fwiw the SRTS is not voluntary on my part, it seems to be a side effect of sw NIDnT muxing

15:05 <Mis012[m]> and the downstream driver's workaround for that seems to have no effect when replicated

15:07 <Mis012[m]> I wonder if the CMD line has some non-standard stuff done to it on the pcb