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<IoTMaker>
very strange, i can connect with jlink commander to my am3352 target, reset, halt etc. works, TopJTAG Probe works also with the Segger/J-Link device, but openocd has some problems and i cannot figure out what exactly the problem is. This is a log from jlink commander https://bpa.st/ICGQE and this is from openocd
<IoTMaker>
https://pastebin.ubuntu.com/p/75QJfFbcNt/ It's still my Rigol DG2052. What parameters do i need to fix this in openocd? Tried a TIAO tumpa, jlink, Olimex Tiny-H and a cheap CJMCU-232H device. None of them work in openocd (default configs).
<PaulFertser>
IoTMaker: this last logs looks like it's working though?
<PaulFertser>
Targets are detected, examined etc.
<IoTMaker>
i tried to go step by step but when the kernel loads i get errors
<PaulFertser>
It halts all right.
<PaulFertser>
IoTMaker: ah, the kernel likely enables sleep modes etc so no wonder you get WAITs there.
<PaulFertser>
Have you seen suggestions to disable cpuidle etc when JTAGing Linux?
<IoTMaker>
until the kernel is loaded, look at line 1573 Error: 76405 74657 adi_v5_jtag.c:522 jtagdp_overrun_check(): Timeout during WAIT recovery
<PaulFertser>
IoTMaker: it looks like it was some time after you used "resume"?
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<IoTMaker>
yes, i resumed and then the kernel is loaded and it shows this error
<PaulFertser>
IoTMaker: so that looks like the kernel reconfigures the CPU in a way that it can't talk over JTAG anymore.
<PaulFertser>
Probably due to frequency scaling or cpuidle.
<IoTMaker>
with jlink commander i can connect later
<PaulFertser>
IoTMaker: probably it reconfigured debug regions somehow without telling you.
<IoTMaker>
in openocd i get the error Target not examined yet when i connect after the system is running
<PaulFertser>
IoTMaker: yes, you usually need to tell the kernel to not interfere.
<IoTMaker>
how can i do this?
<PaulFertser>
IoTMaker: have you already tried “nohlt” or “cpuidle.off=1” ?
<IoTMaker>
that would require to change the eprom content? Thats not an option. I want to get it to work like in jlink commander. It can establish a connection at any time.
<PaulFertser>
IoTMaker: no, why eeprom? Just a kernel command line option.
<IoTMaker>
It loads uboot from spi eeprom and uboot reads the system from nand memory. Maybe i'm too inexperienced. I tought the kernel load command is in the spi eeprom.
<PaulFertser>
But you can change bootargs before running the kernel?
<PaulFertser>
Usually SPI NOR flash memory is used for that, and it's traditionally not called EEPROM as it uses a different protocol and has different size etc.
<IoTMaker>
It is a W25X40, so yes a SPI NOR i guess.
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<Mis012[m]>
well, the main reason SPI NOR is not called EEPROM is that it's not EEPROM
<Mis012[m]>
it's flash
<Mis012[m]>
not that the ROM in EEPROM doesn't stand for "this naming scheme makes no sense"
<Mis012[m]>
u-boot can presumably be stopped and given interactive commands?
<Mis012[m]>
which would mean you can alter the kernel cmdline without changing the flash contents
<Mis012[m]>
also if you're compiling the kernel yourself you can technically add the cmdline arguments with KConfig as a temporary hack
<Mis012[m]>
but that's typically used with bootloaders much less sane than u-boot
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<PaulFertser>
Heh, I thought ROM means just read-only memory. And EEPROM isn't really read-only because it can be erased electrically. So is flash.
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<IoTMaker>
Mis012[m] i can halt uboot, got the password from SPI Flash. I will look for the kernel load command in the SPI dump file
<PaulFertser>
I do not know what magic jlink commander might be doing. Probably some really detailed debug log could tell.
<IoTMaker>
but there is still a problem with reset function because if i halt the am3552 in early stage before loading kernel, i can't do a reset. Reset init tells me: Debug regions are unpowered, an unexpected reset might have happened, JTAG-DP STICKY ERROR, JTAG-DP STICKY ERROR, am335x.cpu: how to reset?
<PaulFertser>
Reset is hard with the SoCs. You probably do not need it.
<phr3ak>
what is DP in JTAG-DP?
<phr3ak>
data port?
<phr3ak>
debug port
<Hawk777>
Debug port, I believe.
<Hawk777>
In contrast to AP, which is Access Port. The DP is kind of the interface to the outside world (JTAG, SWD, etc.), while the AP is the interface to the inside world (the CPU, memory, or whatever). ARM allows one DP to talk to multiple APs, if you have e.g. a multicore chip.
<Hawk777>
In that case it would show up as one JTAG TAP, with one instruction register and one data register, but then commands to the DP are used to select which AP a given command applies to.
<Hawk777>
Even some singlecore chips have multiple APs to handle things like different power and clocking states (e.g. the STM32H743 has one AP that can access pretty much everything but only works when the CPU is running, and a second one that can access only some parts of the chip but works all the time).
<phr3ak>
what is the default state of TAPs? BYPASS?
<Mis012[m]>
it would seem that typically there is an extra AP for direct access to an AHB/AXI bus
<Mis012[m]>
not sure how that works with NoCs
<Mis012[m]>
PaulFertser: well, it's not really read only but it's still part of the name, which is very confusing
<Mis012[m]>
but typically eeprom refers to a specific kind of storage technology
<Mis012[m]>
which is distinct from flash, which is actually a term for storage technology
<Hawk777>
I’m not sure. The ARM debug spec says that if you load any unsupported instruction code into the IR it should be treated as BYPASS, but AFAICT it doesn’t say what the power-up state of IR should be. The JTAG spec might, but I don’t have a copy of that.
<Hawk777>
That would only apply if you do a DRSCAN on powerup without a preceding IRSCAN, which would be kind of weird?
<Hawk777>
As soon as you’ve done any IRSCAN, then you’ve loaded an instruction into every TAP anyway.
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<Mis012[m]>
Hawk777: any idea what my issue might be?
<Mis012[m]>
should be not too far in the backlog, I don't want to copypaste it
<Hawk777>
I’m looking at the logs in the topic, and I can’t see it. There are some messages where you talk about trying “-ap-num 1”, but I’m not sure why, I don’t see any messages in the log with your username on Feb 14 or 15. So I don’t know what the issue is.
<Hawk777>
Then the first message in the log from you today is about naming of EEPROM.
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<Mis012[m]>
Hawk777: the context is trying to get SWD to work on msm8998
<Mis012[m]>
without -ap-num 1 it just hung on examining, now it prints that examination failed
<Mis012[m]>
according to the excerpt that I posted there, it seems that the debug APB bus that should have access to the right registers is on ap 1
<Mis012[m]>
but it still doesn't exactly work
<Hawk777>
Hm, I don’t know what msm8998 is at all.
<Mis012[m]>
a qcom SoC
<Mis012[m]>
sdm835 iirc?
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<Mis012[m]>
Hawk777: should be a quite unique thing for the purposes of fulltext
<Hawk777>
I haven’t really done much with bigger parts like that, I really stick to microcontrollers.
<Hawk777>
I can’t really predict what the problem is with a part I haven’t ever used.
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<Guest60>
Is there an interface driver that I could use to connect to a remote GDB server? For example, using OpenOCD with an ARM fast model?