_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Hammdist> ok I have enabled "bist" and got the read speed 461 MiB/sec, which seems pretty decent
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<Hammdist> are native ports pipelined? in general, is there any documentation on how to interact with a native port (apart from reading the python code)?
<Hammdist> I see by default I get a 128-bit bus, but there are separate valid/ready on cmd and on wdata and on rdata ... looks complicated
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<bjonnh[m]> I'm preparing a class for our local hackerspace on FPGAs and half of it is based on LiteX
<bjonnh[m]> I'm trying to prepare instructions for windows users, and I can't get the colorlight-i5 board to compile properly (works on Linux): http://paste.alacon.org/47741
<tpb> Title: Paste à la con (at paste.alacon.org)
<bjonnh[m]> a simple example with just the litescope works
<Hammdist> found some partial answers to my question here: https://freenode.irclog.whitequark.org/litex/2020-05-14
<tpb> Title: #litex on 2020-05-14 — irc logs at whitequark.org (at freenode.irclog.whitequark.org)
<tpb> Title: Windows setup :: PS1 FPGA Class (at bjonnh.github.io)
<bjonnh[m]> That's what I have for the windows setup
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<SpaceCoaster> bjonnh[m]: I know it isn’t a good solution but commenting out one or both of the add_period-constraint lines for eth_clocks:rx in platforms/colorlight_i5.py worked for me on a Mac.
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<bjonnh[m]> thanks. this is weird there would be such a diff between platforms
<Hammdist> if sent commands on multiple ports, and those commands are largely bulk operations (read/write x, x+1, x+2, ...), does litedram interleave them in a reasonable way when sending them to the dram? by reasonable I mean performance should not drop greatly from interleaving
<bjonnh[m]> <SpaceCoaster> "bjonnh🥬: I know it isn’t a..." <- did you see any impact on the ethernet performance or behavior?
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<bjonnh[m]> Curiously this function is not called at all on Linux
<bjonnh[m]> so I think that's a bug in the argument parsing
<bjonnh[m]> looks like on linux it doesn't go inside generic_toolchain at all
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<bjonnh[m]> Also this bug still exists: https://github.com/YosysHQ/oss-cad-suite-build/issues/42
<bjonnh[m]> Looks like trying a fresh install of OSS-cad and installing Litex in it doesn't work :(
<bjonnh[m]> (on Linux)
<bjonnh[m]> It does the install, I see all the modules in the site-packages of OSS-cad, but I get
<bjonnh[m]> python3 -m litex
<bjonnh[m]> /home/foo/oss-cad-suite/bin/tabbypy3: No module named litex
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<bjonnh[m]> That's the instructions I'm trying to make (that used to work a couple of weeks back): https://bjonnh.github.io/fpga_class_psone/requirements/linux/index.html
<tpb> Title: Linux setup (recommended) :: PS1 FPGA Class (at bjonnh.github.io)
<bjonnh[m]> That seem to work on Ubuntu, but not Fedora...
<bjonnh[m]> Hmm ok false alert that seem to have been some environment pollution
<bjonnh[m]> (I would still appreciate if someones that knows these things could have a look at those instructions and see if they could be improved)
<bjonnh[m]> I think that oss-cad is using a mixture of my local python and the oss-cad one, that's what fails...
<tpb> Title: Paste à la con (at paste.alacon.org)
<bjonnh[m]> I think that's where all the issues stem from, litex when installing is using 3.11 (from my local system) despite me telling it to use the oss-cad environment
<bjonnh[m]> I tried all that on a Ubuntu docker with no python installed and all works well. Except that now I get the same error as I did on windows ( AttributeError: 'NoneType' object has no attribute 'name_override')
<bjonnh[m]> That's the commit that likely broke all that
<bjonnh[m]> SpaceCoaster: ^^ just going back to before those changes solves the issue
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<SpaceCoaster> bjonnh[m]: good one!
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