20:56 <amstan> sigh, why is this so hard? (not litex in particular)

20:57 <amstan> i'm trying to simulate some verilog and run it in the context of a python module and every system out there (verilator, cocotb) has some kind of big blocker

20:58 <amstan> cocotb wants to take over the world and execution context, so i can't just call into verilog and return to some oblivious parent python function with the answer

20:58 <amstan> verilator is all C++ so it's hard to call from python without more wrapper work that needs to be custom coded per verilog module

20:59 <amstan> pyverilator doesn't even run, something sketchy with the tcl libraries it uses

22:00 <mithro> Most of the functionality in these pipelines is implemented by (common) plugins, inspired by the plugin-based design of **VexRiscv**.

22:00 <mithro> https://mici.hu/papers/bognar23proteus.pdf - Proteus: An Extensible RISC-V Core for Hardware Extensions