_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<gurki_> i am either incompetent at doing so or the cpio provided for usage together with the verilator setup is broken - i cannot add anything to it
<gurki_> i could of course build my own, but before i go down that path i would like to verify whether i am incompetent or whether the cpio is actually broken
<gurki_> third option: both :D
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<gurki> im still around, i guess my client is a little confused.
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<cr1901> Hmmm, never seen any issues w/ cpio before. Keep waiting around, obligatory "IRC is async"
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<tpw_rules> the csr.csv is stable right, so long as no python code changes?
<tnt> it's not randomized if that's what you're asking.
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<tpw_rules> nor subject to things like dict ordering?
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