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<qschulz>
macromorgan: 256K is too small IMO. It also doesn't need to be a "ton of overlay" just one that is bringing a lot of nodes or big array properties.
<qschulz>
Kwiboo: so, I am not sure the implem of your pinctrl patches actually is correct. This expects the GPIO indices to be contiguous, and I'm not sure they necessarily are? The naming scheme may be difficult to extrapolate from the actual GPIO index as well
<qschulz>
in any case, I don't think the nr_pins in the controller makes much sense to keep
<qschulz>
if we plan on keeping index contiguity between banks, then it's rather simple to know how many pins there are in a controller
<qschulz>
it's the base of the last bank + the nr of pins in the last bask
<Kwiboo>
qschulz: yeah I know the whole pinctrl <-> gpio bank is a mess :-)
<Kwiboo>
my understanding is that the gpio controller can handle 32 pins, however not all pins are routed/in-use, and for some socs the pins are marked as not-in-use and skipped and others they are not :-S
<qschulz>
Kwiboo: if there's no contiguity, then simply summing up the nr_pins of each bank would be enough I guess?
<qschulz>
Kwiboo: yeah, I vaguely remember some pin in the middle of banks are not routed. E.g. GPIO2_B stops at B4 instead of the typical B7 and the continues at GPIO2_C0 or something like that
<Kwiboo>
if we say that bank nr_pins are the number of pins that are usabe/routed for pinctrl, then your diff probably should be fine, thanks, will test it out later
<qschulz>
Kwiboo: oh yeah, I see what you mean, this also means we're expecting the pin index to be contiguous within a bank
<qschulz>
oof, don't know how we can do in a simple manner except having an array of pins
<qschulz>
or mmmmmm
<Kwiboo>
yeah, there are those holes in the banks, and I think for rk3288 the last 8 pins for gpio0 is unsused and last 16 in gpio8, and for rk3066 there is no gpio5 yet gpio6 exists :-S
<qschulz>
maybe we always have an array of max nr_pins as defined for the bank
<qschulz>
but some entries in the bank can be NULL
<qschulz>
and you shouldn't stop to iterate over, just skip that one
<qschulz>
ah, for non-existing banks.... that'll be interesting to handle
<Kwiboo>
my understanding is that pinctrl driver should expose X number of pins that can be controlled (should idellay match hw), and then the gpio-ranges can be used to configure what pinctrl pin is mapped to what gpio bank pin
<Kwiboo>
so for your example something like gpio-ranges = <&pinctrl 0 64 12>, <&pinctrl 16 76 16>; would mean i.e. pinctrl 64-73 <> gpio2 a0-b3 and pinctrl 74-91 <> gpio2 c0-d7
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<macromorgan>
qschulz: I'm not really comfortable recommending anything larger than 384K today, until we increase the size of the A-TF and that seems to be a lot more work that adjusting a few parameters. 512K technically worked too but with a maximum of no more than 16K more code before things started to choke.
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<qschulz>
I guess 384K is fine? We should check what the alignment requirements are but I believe it just needs to be 8B aligned
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<macromorgan>
I've noted basically how all the fixes link together on this comment here... long story short unless you do all the commits and then make 3 config changes to U-Boot, Optee won't work. But if you do, it'll work just fine: https://github.com/OP-TEE/optee_os/pull/7059#issuecomment-2625252037-permalink
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<CounterPillow>
is the RK3588's AHB bus 64 bits wide by any chance?
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