17:20 <robmur01> lvrp16: with that test I'd imagine you're probably comparing configuration-specific cache performance far more than the CPU cores themselves. According to the upstream DT, MT8186's A55s have L2 which RK3568 doesn't, plus larger L3, so I'd absolutely expect them to perform better in a cache-bound workload

17:35 <wens> not having L2 but having L3 cache sounds weird ...

17:44 <CounterPillow> definitely one of the more cursed implementations out there

20:05 <robmur01> wens: just semantics really - the shared cache in the DSU is L3 by convention since cores *can* have two levels of cache, however if private L2 isn't implemented then the DSU is functionally L2 for those cores

20:11 <robmur01> (the ID registers know and reflect this - https://developer.arm.com/documentation/100442/0200/Register-descriptions/AArch64-system-registers/CCSIDR-EL1--Cache-Size-ID-Register--EL1 )