ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion
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<mriesch>
macromorgan: it's alive. got my first pixels out of my mipi display with your series
<mriesch>
the content is shifted, though, in similar fashion as you experienced
<mriesch>
could you give me a hint what is necessary to get the clocks right?
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<mriesch>
macromorgan: i set the the pll_vpll to 500 mhz and use it as parent of dclk_vop1, as described in your cover letter. content is still shifted, though :-/
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<mmind00>
mriesch: I think the pll rate is somewhat specific to your display ... i.e. first step would be to check what frequency the dsi wants and what it gets in comparison (debugfs/clk/clk_summary and grep for the dclk)
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<hanetzer>
yeh clocking is fun.
<mmind00>
shared baseclocks even more :-D
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<mriesch>
mmind00: ok, i'll have a look at that, thanks!
<mriesch>
(later though, i need to be in a playful mood for that :-)
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<macromorgan>
mriesch: what video port are you using for DSI? and what is the speed reported in /sys/kernel/debug/clk/clk_summary for its associated dclk_vop?
<macromorgan>
for example if you're using VP0, is dclk_vop0 set to (or very close to) your display's pixel clock?
<macromorgan>
pixel shifting was happening to me when it was set to 24MHz instead of the correct pixel clock, which was caused by the HDMI port clobbering my clock settings to set things to its 24MHz reference clock
<macromorgan>
since your board is an rk3568 you should be able to use vp0 for HDMI and vp1 for DSI without encountering the null pointer dereference I was getting
<mriesch>
macromorgan: i am using the combination vp0 <-> hdmi, vp1 <-> mipi dsi. indeed the npe does not occur
<mriesch>
i'll have to check the clock rate later, i don't have the board at hand right now
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<a1batross>
how exactly do you set vpll to 500mhz? I parented vp0 from vpll, though by looking at clk_summary, vpll is set to 24
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<macromorgan>
I add the following (apologies for multi-lines, but IRC...):