01:20 <macromorgan> <a1batross> I'm not sure it matters which vp you use, I do know that 1) there is a bug in mainline that prevents you from using more than 1 VP on the 3566 and more than 2 on the 3568, and 2) vp 1 and 2 don't support resolutions as high as vp0 (nor do they support 10bit color)

01:22 <macromorgan> for clocks, mmind00 says I can't roll back the clock drivers, however I was able to set the default rate of the VPLL at 500000000, and then use that as a parent clock of vp1 for my DSI panel to start working (pixel clock is either 25MHz or 50MHz depending upon 60 or 120hz mode)

01:24 <macromorgan> also, the way the clocks work (at least for DSI, possibly same for LVDS?) is that the VPn gets set to the pixel clock of the interface. For HDMI I think it's set to the 24MHz ref clock, for DSI it's set to the panel's pixel clock.

01:26 <macromorgan> Long story short to set the clock correctly you'll have to define the parent clock of the VPx port you want to use (for me I use HPLL for VP0 and VPLL for VP1). I also have to set the clock frequency of the PLL_VPLL clock to the aforementioned 500MHz

01:26 <macromorgan> sadly I don't have THOSE patches posted yet to show you what I mean, I should have them some time next week though.

13:06 <naoki> today I'm trying rk3568...

13:07 <naoki> it works! (serial console)

13:07 <naoki> ah, gpio led is blinking :D

13:14 <naoki> phy phy-fe8c0000.phy.0: rockchip_p3phy_rk3568_init: lock failed 0x6890000, check input refclk and power supply

13:14 <naoki> hmm...

21:16 <a1batross> macromorgan: so I don't need to set up clk_prepare_enable for DSITX_0 then? My panel is just HD, 71.1 Mhz it should be fine considering VP limits

21:21 <a1batross> I'll try that tomorrow with VP clocks, thanks