00:54 <Attie[m]> 👀

01:10 <M87910[m]> are these the same winbond chips as the icebreaker pmod ram?

01:22 <esden[m]> No these are 1.8v parts

03:09 <jslcom[m]> I don't want to waste anybody's time, and would prefer if there was a way for me to look this up myself, but I'll ask here anyway. I saw above that somebody with order number 177887 has queue position 1836 (out of 2102 orders and 478 shipped). So my order number is 114224, which is 63663 lower than 177887. I ordered a Glasgow Interface Explorer and Glasgow Aluminum case on 2/12/2021. Given the large difference between the order

03:09 <jslcom[m]> numbers, I'll assume that it's a Crowd Supply number and not specific to the Glasgow. Could you please share my queue ID? Thanks a million!

03:12 <josHua[m]> I can give you a lower bound of your queue position, at least: 111784 -> 1074

03:27 <esden[m]> jsl.com (@_discord_511562639357247497:catircservices.org) No problem. Here is your data:... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/iyYpjjtiENzFKmhRRgVQbBZV>)

04:29 <M87910[m]> i'm curious about the lvds connector but it looks like there isn't much documentation for it yet. should i just read the fpga datasheet for things like what impedance the daughterboard should terminate

04:30 <esden[m]> The "lvds" connector is just an assortment of pins we had left on the FPGA package. It is starting to see uses like the RAM-Pak. But it is highly discouraged to be used for regular protocol interfacing.

04:30 <esden[m]> And It is not "lvds" in the LCD sense.

04:31 <esden[m]> It just happens to be able to also output differential pair signals and receive them. The pins can be also used in single ended mode.

04:32 <omnitechnomancer> It is connected to the bank on the FPGA that has differential buffer as an option afair

04:35 <esden[cis]> Catherine: 👀... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/ihkrPLjuNbpGjAlhgHrEPrkF>)

04:37 <Darius> now you gotta use the RAM for something :D

04:37 <Darius> how fast does it ho?

04:37 <Darius> go

04:38 <esden[m]> I don't know how fast Catherine's gateware is. The chips can go 200MHz DDR max according to the datasheet.

04:38 <esden[m]> IIRC the ice40 GPIO max clock is 100MHz?

04:39 <esden[m]> But I have seen people like tnt push even the venerable ice40up5k to faster speeds than that... with a bunch of hand placement yoga but still...

04:41 <Darius> nice

05:22 <Wanda[cis]> the gateware got a timing pass at 90MHz essentially without even attempting optimization

05:35 <esden[m]> Ohh nice! 🙂

06:46 <_whitenotifier-6> [glasgow] whitequark reviewed pull request #549 commit - https://github.com/GlasgowEmbedded/glasgow/pull/549#discussion_r1547227623

10:45 <M246tnt[m]> esden (@_discord_269693955338141697:catircservices.org) Is that script online somewhere ?

10:45 <M246tnt[m]> * somewhere ? ( `test_hyperram.py` )

10:47 <whitequark[cis]> 246tnt: in my branch

10:47 <whitequark[cis]> look at the hyperram pr

16:57 <_whitenotifier-6> [glasgow] neuschaefer synchronize pull request #549: applet.interface.jtag_openocd: implement remote sleep - https://github.com/GlasgowEmbedded/glasgow/pull/549

16:57 <_whitenotifier-5> [glasgow] neuschaefer reviewed pull request #549 commit - https://github.com/GlasgowEmbedded/glasgow/pull/549#discussion_r1548247574