redstarcomrade has quit [Ping timeout: 264 seconds]
umenthum[m] has joined #glasgow
<umenthum[m]>
I'm thinking to use glasgow in maybe a weird way - assuming my DUT is small enough, why not use spare resources on the FPGA to instantiate my DUT and interact with it entirely internally to glasgow - no need to plug in, program, and wire up a second FPGA. Is there any example of this? Specifically it would be something written in Verilog so I think I would use Amaranth's `Instance` but how would I let the applet synthesis flow know it
<umenthum[m]>
needs to pull in my verilog file?
<whitequark[cis]>
Amaranth does not support Verilog files in synthesis
<whitequark[cis]>
err, Glasgow
<whitequark[cis]>
it uses Amaranth in a slightly unusual way that allows it to reliably do caching of bitstreams, and it uses the input as the cache key
<whitequark[cis]>
because of this, it solely considers the RTLIL the input
<whitequark[cis]>
it's not easily possible to do this with Verilog because Verilog files can refer to arbitrary external files via the include directive, $readmemh function, or probably a bunch of other ways I forget
<whitequark[cis]>
you could approximate it, but since caching is mandatory, approximating is not good enough. so it doesn't allow Verilog at all
<umenthum[m]>
ahh interesting. would be nice to have the option to say "well, I'll just forego the bitstream cache and take the time penalty" but sounds like that would be a non-trivial change. I will dust off one of my other FPGA boards 🙂 thanks
<whitequark[cis]>
it's also just completely unimplemented
<whitequark[cis]>
hmm, actually, let me think about it
<whitequark[cis]>
umenthum: nevermind
<whitequark[cis]>
just do platform.add_file("foo.v", "your verilog")
<whitequark[cis]>
the caching will in fact break, so make the filename the hash of the verilog contents or something
<whitequark[cis]>
actually, no
<whitequark[cis]>
make the instance name the hash of the contents of every verilog file
<whitequark[cis]>
or add an attribute to it, or something like that
<whitequark[cis]>
... nevermind#2, it look slike the caching will not break
<whitequark[cis]>
it seems that I've implemented this and then completely forgot that I did
<whitequark[cis]>
oops. sorry!
<whitequark[cis]>
dissociative amnesia is like that sometimes
<whitequark[cis]>
you can add whatever verilog you like with whatever filename and contents and use whatever instance
<whitequark[cis]>
it should all just work
<whitequark[cis]>
tfw your software is too reliable
<umenthum[m]>
haha. I will experiment then
<whitequark[cis]>
good luck
vup2 has quit [Ping timeout: 255 seconds]
koolazer has quit [Ping timeout: 255 seconds]
koolazer has joined #glasgow
vup has joined #glasgow
joerg has quit [Ping timeout: 255 seconds]
joerg has joined #glasgow
notgull has joined #glasgow
notgull has quit [Ping timeout: 264 seconds]
jstein has joined #glasgow
<cyborg_ar>
it's always more fun when you are left wondering why something DOES work instead of doesnt
redstarcomrade1 has quit [Read error: Connection reset by peer]
ar-jan has joined #glasgow
sknebel_ is now known as sknebel
redstarcomrade has joined #glasgow
redstarcomrade has quit [Read error: Connection reset by peer]
josuah has joined #glasgow
bvernoux has joined #glasgow
blward[m] has quit [Quit: Idle timeout reached: 172800s]