whitequark changed the topic of #glasgow to: digital interface explorer · code https://github.com/GlasgowEmbedded/glasgow · logs https://libera.irclog.whitequark.org/glasgow · discord https://1bitsquared.com/pages/chat · production https://www.crowdsupply.com/1bitsquared/glasgow (FUNDED)
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<_whitenotifier-1> [glasgow] brainstorm commented on pull request #285: XC95288XL support - https://git.io/JPCGH
<whitequark> brainstorm: I didn't. I asked azonenberg
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<d1b2> <brainstorm> Thx, I'll try with the corresponding clipped versions then (0x3030 vs 0xaaaa)
<whitequark> didn't vup already figure out usercode bit locations?
<vup> yeah
<vup> they are always in the same column + row in the jed
<whitequark> then why mess with ISE at all?
<vup> but I did not work out how that corresponds to the format you use in glasgow
<whitequark> that format shouldn't exist anyways
<vup> heh
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<d1b2> <brainstorm> So how do usercode_low/high correspond to the XC95288XL? That's the only missing puzzle piece to have https://github.com/GlasgowEmbedded/glasgow/pull/285/files#diff-2db4d5277ba7c919638efd247e16c6917593dca09ef96eb40d1e1f57d77f3710R17 functional and merged I reckon?
<whitequark> take the JED positions that vup has, and convert them to the bitstream positions Glasgow uses
<d1b2> <brainstorm> Oh dear 🙂 ... that's https://github.com/GlasgowEmbedded/glasgow/blob/main/software/glasgow/support/bitstruct.py from what I could follow all the way from read-bit arg on the xc9500xl applet?
<vup> @brainstorm I figured out what is going wrong here: https://github.com/GlasgowEmbedded/glasgow/pull/285#issuecomment-951921045
<vup> the 432 there is actually $NUM_FUNCTION_BLOCK * 108
<vup> and for the xc9572xl which this was written for NUM_FUNCTION_BLOCK is four
<vup> but with the xc95288xl this is 16
<vup> but replacing the 432 with 16 * 108 actually yields the same usercode_low=90 and usercode_high=105 as with the other devices
<d1b2> <brainstorm> Wohoo, thanks @vup! So @whitequark hunch was right with "it's quite possible that USERCODE is always at 90,105"
<vup> fwiw this gives you the jed words for a device with `nfb` function blocks: `[nfb * 108 * row + 8 * nfb * ((8 * col + 6) // 8) for row in range(6,8) for col in range(8)]`
<_whitenotifier-1> [glasgow] brainstorm commented on pull request #285: XC95288XL support - https://git.io/JPWRT
<vup> so you could add support for the xc95144xl aswell, (whose `word_with` would be `64`)
<vup> also fyi im @rroohhh :)
<d1b2> <brainstorm> Argh, I was @-ing the wrong person over github? Sorry :_/
<vup> also I think bitstream_words is wrong, it should be 1620 as all the others
<d1b2> <brainstorm> Ah, good one, I guess that should be a separate PR though.
<d1b2> <brainstorm> Alright, let me test that out...
<d1b2> <brainstorm> % ls -alh cpld_144_with_1620.bit ../../../../cpld_144_foo.bit -rw-r--r-- 1 rvalls staff 101K Oct 25 18:39 ../../../../cpld_144_foo.bit <--- bitstream_words=6420 -rw-r--r-- 1 rvalls staff 26K Oct 29 23:21 cpld_144_with_1620.bit <--- @vup suggestion
<d1b2> <brainstorm> Alright, I'll commit that, you definitely know your way much more through the guts of this thing 😉
<_whitenotifier-1> [glasgow] brainstorm synchronize pull request #285: XC95288XL support - https://git.io/JicYx
<d1b2> <brainstorm> I don't have the IDCODE for the XC95144XL, but I guess it should be sth like 0x9608 by looking at the other variants in sequence?
<vup> the bdsl file says 0x9608 yes
<_whitenotifier-1> [glasgow] brainstorm synchronize pull request #285: XC95288XL support - https://git.io/JicYx
<_whitenotifier-1> [archive] brainstorm opened pull request #8: Add Xilinx xc95144xl datasheet - https://git.io/JPWMn
<_whitenotifier-1> [glasgow] brainstorm synchronize pull request #285: XC95288XL and XC95144XL support - https://git.io/JicYx
<_whitenotifier-1> [archive] whitequark closed pull request #8: Add Xilinx xc95144xl datasheet - https://git.io/JPWMn
<_whitenotifier-1> [GlasgowEmbedded/archive] whitequark pushed 1 commit to main [+1/-0/±0] https://git.io/JPW9i
<_whitenotifier-1> [GlasgowEmbedded/archive] brainstorm 80dbbbe - Add G00082.
<_whitenotifier-1> [archive] whitequark commented on pull request #8: Add Xilinx xc95144xl datasheet - https://git.io/JPW9X
<_whitenotifier-1> [glasgow] whitequark commented on pull request #285: XC95288XL and XC95144XL support - https://git.io/JPWHM
<_whitenotifier-1> [glasgow] brainstorm synchronize pull request #285: XC95288XL and XC95144XL support - https://git.io/JicYx
<_whitenotifier-1> [GlasgowEmbedded/glasgow] whitequark pushed 2 commits to main [+0/-0/±4] https://git.io/JPlIB
<_whitenotifier-1> [GlasgowEmbedded/glasgow] brainstorm a784380 - database.xilinx.xc9500xl: Add XC95288XL and XC95144XL support
<_whitenotifier-1> [GlasgowEmbedded/glasgow] brainstorm 2439f1c - applet.program.xc9500xl: Correct logging stanza for device name and id
<_whitenotifier-1> [glasgow] whitequark commented on pull request #285: XC95288XL and XC95144XL support - https://git.io/JPlI0
<_whitenotifier-1> [glasgow] whitequark closed pull request #285: XC95288XL and XC95144XL support - https://git.io/JicYx
<d1b2> <brainstorm> Thanks to everyone involved in this XC9500XL saga! 😉
<d1b2> <brainstorm> Next up: Figure out how Glasgow's BitStruct works (https://github.com/GlasgowEmbedded/glasgow/blob/main/software/glasgow/support/bitstruct.py), read a bit more about the JED format and convert from each other so that we can interact with @vup's tooling... another time though, sleep() time now.
<whitequark> do you need bitstruct here?
<whitequark> all you need to do, i think, is to merge the "tool" part of the applet into the main code
<whitequark> so that the intermediate .bit format no longer exists
<d1b2> <brainstorm> I don't really know, I was following up read-bit argument from xc9500 and ended up on that class, need to learn more I guess
<d1b2> <brainstorm> Ahaa, I see
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