02:00 <d1b2> <brainstorm> How was "bitstream_words" determined here?: https://github.com/GlasgowEmbedded/glasgow/blob/main/software/glasgow/database/xilinx/xc9500xl.py#L15 ... the datasheet claims 1600 instead of 1620 😒

02:01 <d1b2> <brainstorm> https://www.xilinx.com/support/documentation/data_sheets/ds057.pdf ... "It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates"

02:02 <d1b2> <brainstorm> And the usercode_low/usercode_high? Can't find anything similar comparing the datasheet(s) ... forgive my CPLD-ignorance :/

02:05 <d1b2> <brainstorm> As I mentioned yesterday, I'm adding support for https://www.xilinx.com/support/documentation/data_sheets/ds055.pdf, which claims "6400 usable gates" ... should I add those extra 20 and make it 6420 gates?... are those extra 20 non-usable? How were they determined and how do I make sure there aren't more (or less) in this model?

02:07 <whitequark> brainstorm: everything related to XC9500XL was done with black box RE of programming traces

02:08 <whitequark> https://github.com/GlasgowEmbedded/glasgow/blob/main/software/glasgow/applet/program/xc9500xl/init.py has some details

02:08 <whitequark> I'm afraid there is no actual documentation anywhere that you can just read... though openocd source code may have some useful pointers

02:09 <d1b2> <brainstorm> Ahh, gotcha, will read it thoroughly, thanks much!

02:10 <whitequark> ... i think i was -really- bored at some point

02:10 <whitequark> and had nothing better to do than to reverse-engineer a POST card

02:11 <d1b2> <brainstorm> Hey, those usually turn up to be the best projects, nothing bad with being bored every now and then 😉

02:12 <whitequark> the interface of that applet is really weird, requiring you to use a Glasgow-specific intermediate format

02:12 <whitequark> and an explicit conversion tool

02:12 <whitequark> dunno what i was thinking, that's silly

02:13 <d1b2> <brainstorm> My boredom with this particular CPLD is some camera link framegrabber card from a DNA sequencer: https://www.hackteria.org/wiki/HiSeq2000_-_Next_Level_Hacking

02:13 <whitequark> oh that's really fascinating

02:13 <d1b2> <brainstorm> Will see how far I go, just getting acquainted with its architecture

02:13 <whitequark> if you need assistance with RE ping me anytime

02:13 <whitequark> i've actually completely RE'd another CPLD family at one point

02:13 <whitequark> https://whitequark.github.io/prjbureau/

02:14 <d1b2> <brainstorm> Woot, <3, will do, thanks a lot 😉

02:16 <d1b2> <brainstorm> The crown jewel of that board is a Spartan 6 though, the CPLD seems to be only doing some RAM multiplexing, we can discuss some details in private if you are really keen, feeling a bit nervous of putting more stuff I've found in the open... but regardless, I'd like to put support for whatever I need along the way into Glasgow, I'm loving the board so far 😉

02:17 <whitequark> there's support for XC6S too!

02:17 <d1b2> <brainstorm> I know! ;)... says preview quality, I'll get there, but one step at a time 🙂

02:17 <whitequark> i don't quite remember what was preview quality about it

02:18 <whitequark> code looks okay, really

02:20 <whitequark> the hesitation is understandable, i think i'm not going to get involved much at the moment, have enough stuff on my plate

02:20 <whitequark> but i certainly can support you with the knowledge i have

02:25 <d1b2> <brainstorm> Fantastic! I'll try to self-direct with what's available out there with your pointers and not bother you too much for now, thanks for everything you are doing!