03:03 <d1b2> <brainstorm> That __init__.py RE documentation for the XC9572XL was very interesting... I first went for the naive way and change the parameters I know so far for the XC95288XL, but it clearly needs more understanding, since I cannot go with the usercode_low/usercode_high settings as-is... the word_width should be 16 as specified in the datasheet though. Here is a basic diff and the first backtrace:

03:03 <d1b2> https://hardbin.com/ipfs/QmfC2n9t5dDnwLfZghcrAFTJ7mPTjPxGAoow767wMYTgsz/#zrazi6DackZJYS7NqiQCq2BNShbQTUGbKR2T8JZnXx1 I also installed the Xilinx ISE 14.7 suite but does not have a single XC95288XL-specific example design, so I'll guess I'll have to cook a simple one myself... WIP

03:05 <d1b2> <brainstorm> From what I understood, the RE was based on the JED/BSDL files, no "Xilinx platform cable" and (USB?) sniffing should be needed I guess?

04:48 <whitequark> no, it was also based on poking a real CPLD

04:48 <whitequark> I actually didn't touch ISE or anything Xilinx-related (except for the target) at all

04:50 <whitequark> at the very least, I think XC95288XL will use a different word width

04:50 <whitequark> wait, you took it from the -datasheet-?

04:50 <whitequark> which part of the datasheet specifies that?

04:53 <whitequark> okay, so XC95288XL specifies a 130-bit ISDATA register

04:53 <whitequark> this means word_size=128 for that device

05:12 <whitequark> oh, correction: to get usercode_{low,high} I asked azonenberg to generate a pair of

05:12 <whitequark> bitstreams

05:12 <whitequark> other than that it was just me, BSDL/JED files, and the device