17:53 <d1b2> <dsp8bit> I didn't mention as a solution for the clock domain crossing, it is just an idea for a feature that i would like to have in a Glasgow. I've been working with a FIFO design for transceiver, the LMS6002, and the clock domain crossing and simulating the real behavior is complicated for different cases of clock domains. I recommend this paper of Clifford E. Cummings http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf, as I

17:53 <d1b2> understand, this i already considered in nMigen. That's why i would like to play with glasgow with different clock domains. I don't have a Glasgow yet, but i will be interesting.