21:18 <d1b2> <xabean> fast forward 11 years: ... "via a surprise stock market crash, a quick conversion of DEFCOIN to mutual funds, followed by a stock market bounce back. That's the story of how 1b2 became our own silicon fab."

21:21 <d1b2> <sys64738> (now to convince all the IC companies to send their masks to you)

21:39 <d1b2> <tnt> @kbeckmann I haven't seen it mentionned in the backlog, but revB 's interface to the FX2 is clocked slower than on revC, so lower bandwidth is expected.

21:41 <d1b2> <kbeckmann> oh! i didn't know that. that would explain what i am seeing.

21:43 <d1b2> <tnt> 30 MHz for revB and 48 MHz for revC

21:44 <d1b2> <kbeckmann> yeah that seems to match the performance i got as well. 30e6/1024/1024 is 28.6, and I got around 27-28 MB/s

21:53 <d1b2> <kbeckmann> what is the reason for the clock being lower on RevB? is it harder to match timing on that FPGA? UP5K vs HX8K

21:58 <d1b2> <kbeckmann> i suppose so. it doesn't seem possible to get a glasgow design using the fx2 fifo much faster than 35MHz.

21:59 <sorear> the up5k fabric is more than twice as slow

22:03 <d1b2> <kbeckmann> alright. i tried with some custom yosys and nextpnr flags and was able to reach 48.31 MHz for the benchmark applet. so yeah this will not be so fun when you are trying to do something useful with it as well 🙂

22:15 <d1b2> <kbeckmann> nice, managed to "overclock" it to 48 MHz and the benchmark now runs at around 40 MB/s

22:45 <d1b2> <kbeckmann> in case anyone is curious i put the patch here https://gist.github.com/kbeckmann/2161c7f9cfa2c2ff86fbe28ec8c1994b

22:48 <d1b2> <kbeckmann> is there an easy way for me as a human to find out if my fifo has ever been filled completely? it would be nice to e.g. light up the error led with a timeout of e.g. 1 second.