<davidlt>
I guess that they cooked X60 as intermediate milestone as X60 is not RVA22 (I think)
<davidlt>
conchuod, ISA seems to be: rv64imafdcvsu_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf
<davidlt>
Their X100 seems to be more powerful on vector side compared to P670 (at least by numbers).
<davidlt>
SiFive P670/P870 has VLEN 128-bit and 2 vector units/pipeline IIRC
<davidlt>
X100 (if that happens) has VLEN 256-bit and 4 * 128-bit units IIUC
<conchuod>
davidlt: right, can't say I've ever heard of that core.
<conchuod>
No h on any of these things yet :/
<davidlt>
conchuod, yeah, X100 is suppose to have it
<davidlt>
I think I saw it in their code
<rwmjones>
hezhengyu: will look shortly
<rwmjones>
davidlt: done openmpi; for the f40 branch, I will just backport the commit once it has gone into rawhide (and same across other packages too)
<davidlt>
rwmjones, thanks
<rwmjones>
davidlt: ok I did all those packages from yesterday
<davidlt>
rwmjones, patch was posted by Intel to add QEMU server platform reference machine (RFC)
<davidlt>
the only out-of-tree thing was ACPI IIUC
<davidlt>
rwmjones, you might want to ping some folks about it
<davidlt>
Oh, there is AST2700 chip
<davidlt>
Heinrich from Canonical already commented on QEMU RFC patch.