ChanServ changed the topic of #armlinux to: ARM kernel talk [Upstream kernel, find your vendor forums for questions about their kernels] | https://libera.irclog.whitequark.org/armlinux
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<markussp> robher: Hi Rob, you mentioned on my chipid nvmem binding patch that it is not compatible if there is a completely different way of accessing the data. I am not really sure how to solve your comment or move forward? Would you suggest a different compatible or something else?
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<ajb-lina-> maz_ is 20231208164709.23101-1-ankita@nvidia.com the relevant series about messing with cachability bits? or is there a newer one?
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<maz_> ajb-lina-: it is that, although as j`ey points out they have just rebased it.
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<dmart> maz_: Hi, what's the current state of nVHE? I'm wondering how much we still have to for trap controls in EL2 on the boot/resume paths, for new features.
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<maz_> dmart: hey, nVHE/hVHE is alive and kicking, so we still need to deal with it for new feature enablement.
<dmart> maz_: OK, still trying to understand the sleep/resume end of it.
<dmart> maz_: For stuff that we enable based on cpufeatures and then never touch, is it enough just to add stuff to finalise_el2_state?
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<dmart> maz_: (hmm, maybe cpufeatures doesn't come into this)
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<mathew51> Hello, for a GIC-v3 system how do we determine the GICR base and length?
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<maz_> mathew51: from the TRM. there is no discovery mechanism to find the valid ranges (note the plural, there may be more than one).
<mathew51> maz_:  thanks, so I just need to keep looking for matching GICR_IIDR values then.
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<maz_> dmart: probably enough to stuff things in finalise_el2_state, but you need to find that on a per-case basis, but this is also used in the VHE case (see __finalise_el2)
<mathew51> maz_: size allocated to the SoC for GIC is 2M, so should  I assign the remaining size to GICR or keep the size of GICR to 10000 (based on GICR_CIDR3 reg)?
<maz_> mathew51: checking for GICR_TYPER.Last should help finding the upper bound.
<maz_> mathew51: I'm not sure why CIDR3 should come into play. a single RD frame is 128kB for GICv3 (256kB for GICv4), and that's an architectural constant.
<mathew51> maz_: thanks for the pointer, ill look at GICR_TYPER dump.
<maz_> so if you have the base of a RD block, you find the architectural version, and skip by 128/256kB until you find TYPER.Last being set.
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<mathew51> maz_: gotcha, thanks!
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<dmart> maz_: Is there a cheat sheet for understanding the main VHE versus nVHE boot paths?
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<maz_> dmart: the basic principle is that if nVHE is supported, we start with that, and then upgrade to VHE in __finalise_el2() if that's what we want. But if the CPU isn't nVHE capable (E2H RES1), we drop to EL1 as a *guest*, and only later decide whether we want to upgrade to running at EL2 or not.
<maz_> so there is a distinction between supporting VHE/nVHE, and running in that mode.
<maz_> on a VHE system, you can run VHE (kernel and HYP at EL2), hVHE (kernel at EL1, hyp at EL2 in VHE mode), nVHE (kernel at EL1, HYP at EL2 in nVHE mode).
<maz_> on a nVHE-only system, only the last part is possible.
<maz_> on a system that doesn't have FEAT_E2H0, that last part is not possible.
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<j`ey> maz_: for hVHE does it use the same code as the nVHE part in EL2?
<maz_> j`ey: almost. the control registers are slightly different, the page table format is different, and this is going to keep evolving.
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<j`ey> I should look at the commits that introduced hVHE
<dmart> maz: ^ thanks
<maz> j`ey: yeah, it's pretty small for now. I have bigger plans, but that's for when NV is done. one day.
<dmart> j`ey: I may pick your brains on this too...
<j`ey> dmart: I can try help!
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