09:34 <_whitenotifier-9> [amaranth] kivikakk opened pull request #1401: docs/guide: remove extraneous "not only". - https://github.com/amaranth-lang/amaranth/pull/1401

09:36 <_whitenotifier-9> [amaranth] codecov[bot] commented on pull request #1401: docs/guide: remove extraneous "not only". - https://github.com/amaranth-lang/amaranth/pull/1401#issuecomment-2171330206

20:45 <Hoernchen> is there a pretty way to abuse amaranth to generate verilog testbenches? i'm using a clarity designer generated mac Instance("foo",..), so pure python sim doesn't work, so i tried the opposite approach by going for all verilog using verilog.convert_fragment which works fine as long as there are ports, but.. my tb does not/should not have ports..

21:06 <whitequark[cis]> what do you expect to be in a generated testbench?

21:07 <_whitenotifier-9> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-1401-af4e4a748950e3ab8d144ec56bf066449a524c46 - https://github.com/amaranth-lang/amaranth

21:10 <Hoernchen> just basic sync stuff, nothing fancy, that drives the dut +- maybe one initial statement for dumpvars

21:11 <whitequark[cis]> amaranth won't generate a behavioral testbench for you

21:11 <whitequark[cis]> so no $dumpvars, no $finish, nothing like that

21:13 <_whitenotifier-9> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth/compare/af4e4a748950...0915b9a043f8

21:13 <_whitenotifier-9> [amaranth-lang/amaranth] kivikakk 0915b9a - docs/guide: remove extraneous "not only".

21:13 <_whitenotifier-9> [amaranth] whitequark closed pull request #1401: docs/guide: remove extraneous "not only". - https://github.com/amaranth-lang/amaranth/pull/1401

21:13 <_whitenotifier-9> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-1401-af4e4a748950e3ab8d144ec56bf066449a524c46 - https://github.com/amaranth-lang/amaranth

21:14 <whitequark[cis]> you could of course write some RTL to drive another design, just like you'd do it for synthesis

21:14 <Hoernchen> yeah, i have settled for generating the not-tb and then wrapping that in a small python generated verilog template, and then uh.. driving all of that using cocotb..

21:14 <whitequark[cis]> and then add a stub testbench that drives a clock, does $finish and so on

21:14 <whitequark[cis]> yeah. so for the next release we plan to add CXXRTL support, which will let you simulate instances

21:14 <_whitenotifier-9> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-0/±40] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/aeb4d2350615...3ff1eba61acf

21:15 <_whitenotifier-9> [amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 3ff1eba - Deploying to main from @ amaranth-lang/amaranth@0915b9a043f8c8c6511a8e398948d93b82f92bbf 🚀

21:15 <Hoernchen> mmh yes, cxxrtl was the other idea i had: what if i compile my generated verilog and then load that somehow...

21:15 <whitequark[cis]> the cxxsim branch does exactly that

21:16 <Hoernchen> oooh

21:17 <whitequark[cis]> but it's rather unfinished and very "when it breaks you get to keep all the parts"