<byteit101>
What's the preferred way to do range checks (ex. vga rows/columns)? Does amaranth support python ranges as a case statement? or should I just do the traditional verilog >= <=, etc operators?
<d1b2>
<josuah_dem> My coarse understanding is that it can be seen as an equivalent to multiple "with m.If (value == XXX):, here value is the same everywhere, and XXX changes from one m.Case()` to another
<byteit101>
Eh, looking at the doc, it looks like very little is supported, thus newb and mid-tier developers may think the ceiling is pretty low and to just go learn another HDL. By showing something, even if it's slightly out of date, newbs will be confused, but mid-tier will likely be able to muddle through, increasing the install base and mindshare, and increasing the # of people that want to help keep doc up to date. it's a vicious
<byteit101>
or cycle
<byteit101>
When I asked previously if I could help just add "this exists" to the doc, I got a NO, and that's not helpful
<josuah>
byteit101: there is quite a few doc available through the source itself in the python docstrings, but it is not being rendered still.
<byteit101>
wait, hmm, do I need to specify the files?
<josuah>
that gives some kind of crude reference, but it is not a separate browsable doc either.
<josuah>
byteit101: not perfect for discovering "how do I X", but in my personal experience, looking at the source revealed that most of Amaranth is a small set of core types (defined in hdl.py), down to which everything is reduced to
<josuah>
Instance is likely one of them (a special case rather than the "core language" eventually)
<josuah>
knowing this, when looking at something new, figuring out how it maps to the core types helps with understanding within the lack of doc
<byteit101>
Hmm.. how can I add an array of submodules?
<byteit101>
without typing it fully out
<josuah>
byteit101: you could use a python loop
<josuah>
unlike other python-based languages such as MyHDL, amaranth's language construct are clearly separate from python's own syntax
<byteit101>
for elt in list: m.submodules.??? = elt
<josuah>
yes exactly, and there are a few constructs to allow programmatically give a name to the modules
<byteit101>
Do you have any examples?
<josuah>
let me grab these...
<josuah>
m.submodules +=
<josuah>
Then you do not need to specify a name, just instantiate the submodule there to add them as an array.
<byteit101>
Ah, great!
<byteit101>
Thanks
<josuah>
You would have to instantiated the module first, and wire it with the context, as once added, it would not have a name anymore, so not possible to access its contents as m.submodules.xxxx.signal
<josuah>
extra resource that can be useful with amaranth: for all these fresh features that were just adopted and not yet documented, there are the RFCs: https://github.com/amaranth-lang/rfcs
<adamgreig[m]>
Catherine: lol, my software crc is decently faster than the lookup-table-optimised `crc` library implementation, and much much faster than its equivalent bit-serial implementation, so I guess there's really no point trying to integrate with it
<adamgreig[m]>
(faster even totally excluding the extra time crc takes to generate lookup tables when you use that version)
<adamgreig[m]>
however the crcmod library, which has a c extension, is orders of magnitude faster again, unsurprisingly. still I think this is probably fine for amaranth
<byteit101>
Ah yes, that seems to work
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<d1b2>
<Nate> wow, the generated verilog is so much more readable when using e.g. m.submodules.fifo = fifo instead of m.submodules += fifo