<WilliamDJones[m]>
I feel like the default `sync` domain on ECP5/MachXO-whatever occupies a niche that's not quite `reset_less=True` and not quite `reset_less=False`. `reset_less = "handled_by_primitive"`? Idk...
* WilliamDJones[m]
can't words tonight
<whitequark>
it's never reset_less
<whitequark>
reset_less means there's no reset. there is always a reset, but without default_rst it's connected to the end-of-startup signal
<WilliamDJones[m]>
> As such, the sync domain is reset-less, along with `reset_less=True` on line 220
<WilliamDJones[m]>
<WilliamDJones[m]>
And `reset_less=True` here is of course correct. I just think I would've worded the comment something like "this domain has a reset signal handled externally, so we don't need reset logic generated, thus set `reset_less=True` for this specific case".
<WilliamDJones[m]>
> As such, the sync domain is reset-less
<WilliamDJones[m]>
Along with `reset_less=True` on line 220. And `reset_less=True` here is of course correct. I just think I would've worded the comment something like "this domain has a reset signal handled externally, so we don't need reset logic generated, thus set `reset_less=True` for this specific case".
<WilliamDJones[m]>
(But hey, that just reflects how I went about understanding the code and asking in here. My experience not necessarily typical :P.)
<WilliamDJones[m]>
<whitequark> "if it's ever asserted for less..." <- Btw, can you elaborate on this? If my UART BRK is synchronous and held for one cycle, _assuming `GSR` can reach the entire chip in a single cycle w/o setup and hold violations_, what glitch can occur?
<d1b2>
<VA3TEC-Mikek-14362> I am working on the DE1-Soc board and want to get the 7 segment displays up and running. But I am having trouble getting the platform nomenclature correct. in the Amaranth_Boards file they specify the display this way. Display7SegResource(0, a="AE26", b="AE27", c="AE28", d="AG27", e="AF28", f="AG28", g="AH28", invert=True, attrs=Attrs(io_standard="3.3-V LVTTL")),
<d1b2>
<VA3TEC-Mikek-14362> yes yes, ok i was looking in the wrong place... makes sense now... I was looking under res.. for resources.
<d1b2>
<VA3TEC-Mikek-14362> thanks Josuah!!
<d1b2>
<VA3TEC-Mikek-14362> @josuah_dem If I am not mistaken, your project is the pico-ice-pmod project, but you are defining the pmod pins directly in the file pmod_7seg.py.
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<d1b2>
<VA3TEC-Mikek-14362> I see that you separate the com and the seg (segment) pins. Do I need to do that for the DE1-Soc board? I see a lot of examples using the Pmod pins, but not the "amaranth_boards" directly method. I could specify them separately, but I want to avoid doing that.
<WilliamDJones[m]>
>it's not a timing violation, just a single cycle glitch
<WilliamDJones[m]>
Are you talking about how the AND/OR gate can toggle (due to LUT implementation) before settling on the final value? I still don't see the problem; async reset parts of my circuit (_there are none_ atm) gets the reset asserted/released some fraction of a clock cycle earlier than the sync reset parts.
<d1b2>
<VA3TEC-Mikek-14362> I figured more out! I got something to work!! 🙂 the other example that I was using was multiplexing the the digit's, But the DE1-SoC board has ALL the pins connected to the FPGA, so no multiplexing needed.
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<d1b2>
<josuah_dem> Yes, I should have been using the pmod_7seg.py
<d1b2>
<josuah_dem> But the Pmod library from amaranth is a bit out of date I think.
<d1b2>
<josuah_dem> the specification got updated
<d1b2>
<josuah_dem> with a bit more interface types
<d1b2>
<josuah_dem> Very glad you did! I had a phone call in-between.
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<d1b2>
<VA3TEC-Mikek-14362> No worries! I was in the garage getting my 40 amps, 240V volts installed for my plasma cutter. 🙂
<d1b2>
<josuah_dem> Whoa! That must be something! 😄
<d1b2>
<VA3TEC-Mikek-14362> Sheet metal, I am trying to make a sheet metal lab in my garage, I have it connected to the computer, CNC. and the TIG welder. etc. etc.