<d1b2>
<Nate> how feasible / problematic is using the generated verilog to port modules between amaranth <-> migen / verilog systems? I assume there are no gotchas I should know about?
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<whitequark>
the main gotcha is "Verilog" to be honest
<d1b2>
<josuah_dem> For debug, I also use the Yosys intermediate representation file generated by Amaranth (named build/top.il) which is quite verbose, but still allows me to check "what value do I end-up in the end? did Amaranth synthesize that block inside that compile-time python if, ...)