whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<_whitenotifier> [amaranth-boards] JarrettBillingsley commented on issue #207: Upgrading from nMigen and cannot get amaranth-boards installed - https://github.com/amaranth-lang/amaranth-boards/issues/207#issuecomment-1328151336
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<Guest48> is there a way to define an instance from a verilog file? Something like Instance_from_file("foo.v").
<Guest48> Of course it can do port inference and allow me say: "give me all axi initiator interfaces" etc it would be great.
<Guest48> similarly if I can interrogate the parameters of the module etc. it would be nice.
<tpw_rules> you're familiar with regular Instances, right?
<Guest48> other than one example I saw, not really. I'm very new to nmigen/amaranth.
<Guest48> what can I read, what examples exist?
<Guest48> that's the example I saw. I don't want to type in the ports, parameters, attributes etc. I want them to be parsed/inferred from the verilog file; like if you have 5 ready-valid channels with these suffixes & directions, it might be an axi-initiator etc.
<tpw_rules> afaik that's not possible
<Guest48> Basically I'm looking for something like magma's m.define_from_verilog_file
<Guest48> It would be a great feature if it existed and would make integration much easier.
<Guest48> has anyone looked at https://github.com/sifive/duhportinf
<Guest48> another q: has anyone written something like a datamover in amaranth?
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