whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<_whitenotifier> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/ffe8ccfaacc6...829ba1d19f36
<_whitenotifier> [YoWASP/yosys] whitequark 829ba1d - Update dependencies.
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<KiranShila[m]> What is the equivalent way of doing `fs_shift5_model_o <= repeat (5) @(posedge clk) fs_model_o;`?
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<whitequark> there isn't; is that even synthesizable?
<whitequark> (I'm guessing you are writing a testbench, but just to make sure)
<tpw_rules> i think it's a little undocumented, and i'm not confident i understand your verilog, but maybe m.d.sync += fs_shift5_model_0.eq(Past(fs_model_o, 5))?
<KiranShila[m]> I’m also not very familiar with verilog, but I saw this as an example to create a 5 cycle delay
<whitequark> I think that might not be synthesizable
<KiranShila[m]> Haha alright
<KiranShila[m]> Is there another way you’d recommend creating a n-cycle delay?
<whitequark> so it boils down to creating a chain of n flops, right?
<KiranShila[m]> Right
<whitequark> you can do this by creating n Signals, or a n-bit Signa
<whitequark> s/Signa/Signal/
<whitequark> Amaranth is a low-level language that doesn't have things like inference from behavioral constructs
<whitequark> if you want a few flops, you have to define them yourself, essentially
<KiranShila[m]> Ah the n bit signal makes sense, then do shifts every cycle
<KiranShila[m]> I’ll give that a shot
<whitequark> yeah. `m.d.sync += Cat(o, shreg).eq(shreg, i)`
<whitequark> * Cat(o, shreg).eq(Cat(shreg, i), * shreg, i))`
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<KiranShila[m]> is there any way to prevent the creation of duplicate identical modules in the emitted verilog?
<KiranShila[m]> For example, I have two instances of a the same module in my circuit, each of which have their own submodules. Then, after generating verilog, I end up with a module definition for every submodule and for every child submodule, etc.
<whitequark> no
<whitequark> what Amaranth emits is essentially equivalent to a post-elaboration Verilog netlist; that is, a Verilog toolchain creates the same representation internally almost immediately after it reads your source code
<whitequark> you can think of the Amaranth Verilog output being slightly more preprocessed than the hand-written Verilog you would normally feed to a toolchain
<KiranShila[m]> Makes sense
<KiranShila[m]> The escaped names break the perl library I was using to split the modules, which I suppose makes sense because then the filenames would get kinda hairy
<whitequark> I think that is strictly a bug in the Perl library
<whitequark> the escaped names are a Verilog-1995 feature
<KiranShila[m]> Yeah of course
<KiranShila[m]> I think I'm XY Problem-ing myself here trying to split the modules
<KiranShila[m]> The only reason I was doing it was because I'm using the output as a black box in (god forgive me) Simulink
<whitequark> the desire to have split verilog output is a common one but unfortunately the current architecture is not conducive to it
<whitequark> it will be eventually implemented
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<bentomo> Nah nothing that extreme, I just want to comply with open source licensing and give credit where it's due.
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