_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<notdavid> so I'm a little stuck on adding a wishbone slave to the main bus. I have an SoC w/ a vexriscv (basically a carbon copy of the colorlight i5 with a couple things removed). I've made a dumb wishbone LED thing in verilog, hooked it up through a migen Module, with all the wishbone signals, rst, and clk (via ClockSignal and ResetSignal), then made a
<notdavid> new wishbone interfaced, connected the pins, created a new memory region (inside the IO memory region? I'm unsure about this, I did it because it complained that it had to be cached unless it was in the IO region), and added a wishbone slave.
<notdavid> Here's a gist with the relevant code: https://gist.github.com/davidlenfesty/1d301f2769c8f2ba77098e50ded77e11
<notdavid> I'd appreciate if anyone could give me pointers, I'm sure I'm just missing some concept I could find if I went looking in the right place.
<notdavid> (err, my symptoms were being able to read/write some cached value, but that was due to a dumb mixup in my testing FW, hitting different behaviour so idk if anything I could say is still valid)
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<notdavid> okay, pretty clear from the generated verilog none of the wishbone signals are getting connected at all
<notdavid> gave up and switched to CSRs, and now the cpu hangs when I write to the CSR address ¯\_(ツ)_/¯
<MoeIcenowy> mithro: do you mean let me upstream the changes?
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<mithro> MoeIcenowy: yeah, they might also tell you how they expect the include stuff to work
<MoeIcenowy> mithro: they expect some of the directories to be added to the synthesis program's include dir
<MoeIcenowy> which isn't applicable on some platforms
<MoeIcenowy> e.g. Quartus
<tpb> Title: Solved: Search Path for Source Files - Intel Communities (at community.intel.com)
<MoeIcenowy> mithro: well I remember I failed on it
<mithro> I haven't used Quartus, so no idea
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