sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<courmisch> why are kernel optimisations manually aligning code to 8 bytes at internal jump labels?
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<Esmil> drewfustini: i don't know if you remember, but i spent so much time trying to get bluetooth working with the in-kernel driver on the Starlight board. i finally solved it \o/
<Esmil> it may be obsolete by now, but it still feels good to solve a 2-year old mystery :)
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<drewfustini> Awesome, good to hear!
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<YangyuChen[m]> I have benchmarked specint 06 on spacemit X60: https://blog.cyyself.name/spacemit-x60-k1-specint-2006-benchmark/
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<Esmil> YangyuChen[m]: are you saying the C910 on the TH1520 is faster than the core on the K1? (except maybe it's maybe less buggy and if you're heavy user of the vector/etc. extensions)
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<YangyuChen[m]> <Esmil> "Yangyu Chen: are you saying..." <- I would say yes for SPECINT 2006. For some workloads that benefit for Vector, I think it will not, such as my openssl patch for chach20 rvv support.
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<YangyuChen[m]> Note that Spacemit X60 is an dual issue in-order core. It has no out-of-order execution.
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<Esmil> YangyuChen[m]: interestin, thanks
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<drewfustini> YangyuChen[m]: thanks for sharing
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<drewfustini> I'm curious do you know what mvendorid, marchid and mimpid are on the X60?
<courmisch> yeah I think a lot of asm optimisations were written with OoO in mind and either not benchmarked or only on T-Head C908/C910/C920 :/
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