azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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Hi everyone! Has anyone used yosys to synthesize for Gowin FPGAs ? I'm having problem synthesizing VexRiscV soft-core.