azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
<iobus>
problem solved maybe? i removed async reset in my module and it works, why? IDK
<iobus>
if you are reading this from google search log, the fancy async reset in your modules from your textbook might be the issue in ice40
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