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famubu[m]>
Hi. I'm using yosys to synthesize a small design on to a gowin fpga (on sipeed tang nano 9K).
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famubu[m]>
Despite a lot of registers being available, yosys seems to use LUTs to make registers instead.
<
famubu[m]>
Is there a way to indicate to yosys to use registers themselves if available and resort to making registers out of LUTs otherwise?
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tnt>
famubu[m]: wdym yosys is making registers out of luts ?!?! What makes you think that ?
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Adrien[m]>
Latch implementation perhaps ? Intended register file in distributed logic ?
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famubu[m]>
I was checking the log made by yosys during synthesis.
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famubu[m]>
When I increase the size of the design, the LUT count goes up but FF count remains same.
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famubu[m]>
So I figured it's using LUT to implement registers. That was a guess. Am I wrong there?
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famubu[m]>
The 'printing statistics' part of the yosys log.
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famubu[m]>
Wait.. I might have been looking at the wrong log..
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