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<Guest2>
yop, I'm curious if yosys+nextpnr-ecp5 is able to use a block ram with output register configuration. I'm unfamiliar with those tool, but if I understand well the code here https://github.com/YosysHQ/yosys/blob/main/techlibs/ecp5/brams_map.v#L120 it seems that it's always inferred without output register?
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<Adrien[m]>
Hi all, does anyone have a declaration for primitive PS8 ?
<Adrien[m]>
Or a hint on where that can be found or generated
<Guest2>
I have designed a riscv5 multi-stage, multi-hart as barrel processor. I'm using xiling vivado in parallel to crash-test my design. with vivado and targeting an xc7 or xcvu9p, adding an extra delay register after reading a block ram greatly improve timing. but with yosys for ecp5, it increase only slightly, and next-pnr both suggest that the bram
<Guest2>
read registers are in the critical path. stuck at ~115MHz
<Adrien[m]>
vivado-generated wrappers are too much of a pain to manually process to get to a clear declaration... (vhdl preferred, but clear verilog would be great too)
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<Adrien[m]>
I was thinking maybe Yosys could have a sort of database of primitives, or taking it from prjxray, but it's not obvious
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<Adrien[m]>
granted, there are quite clear PS8 module declarations un Yosys repo, but ports are sorted by direction instead of by "channel", so more processing needed to reorder according to vivado-generated order, which is more human friendly.
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<uis[m]>
In what state xc7 pnr?
<uis[m]>
How hard and feature complete opensource design flow for zynq7?
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<Adrien[m]>
ok sed and grep will make it work eventually...
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