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<Adrien[m]>
Hi, I have an issue with how Yosys manipulates Variable Parts Selects, in verilog.
<Adrien[m]>
This is recognized as a mux and is synthesized as a mux : input [3:0] sel; input [15:0] idata; assign odata = idata[sel +: 1];
<Adrien[m]>
This is 1b selection so the direction should not matter. Let's change +: to -: and give it to Yosys : input [3:0] sel; input [15:0] idata; assign odata = idata[sel -: 1];
<Adrien[m]>
With -: the generated netlist for Xilinx xc7 is 5 LUT6, instead of the expexted 4 LUT6 + some in-slice muxf.
<whitequark[cis]>
for any verilog issues, try using https://github.com/povik/yosys-slang instead of the built-in frontend and see if that still reproduces
<Adrien[m]>
Is there a subtlety in what these syntaxes mean, or could this be considered an issue in yosys somehow ?
<Adrien[m]>
Catherine: Yes I'll try that.
<Adrien[m]>
Tried : it does work with slang plugin ! 👍️
<Adrien[m]>
If there are people relying on Yosys parser, this deserves a fix. Should I open a bug report ?
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<Guest77>
can yosys do simplifying combinational logic circuits?
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