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<juri_>
Is there an authoritative list of all of the nextpnr-XXXXXX projects, and what their current status is?
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<lofty>
juri_: no, but as a nextpnr dev I can give you one? :p
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<juri_>
lofty: I'm currently looking to see if anyone is working on the spartan 6, virtex 4, or stratix 5.
<juri_>
with a minor interest in the cyclone 4.
<lofty>
no, no, no, and no respectively
<lofty>
:p
<juri_>
can i ask again, and get different answers? :)
<lofty>
If you ask about the cyclone v, perhaps?
<juri_>
lost my bid on one of those. :)
<lofty>
Spartan 6/Virtex 4 requires xilinx ISE RE, which has been done, but nobody's contributed an architecture for those
<juri_>
you wouldn't know anyone with an ISE 6.3 license they want rid of... :)
<lofty>
See, I'm nominally team lead of the cyclone v RE project
<lofty>
the iv is kind of out of scope because it's majorly different to the v
<lofty>
the stratix v... might be doable if we could source quartus standard
<juri_>
I... am doing that.
<juri_>
it's bloody expensive, but i'll get it done.
<lofty>
I mean, granted, nextpnr struggles with the Cyclone V for a number of reasons (do you want the long explanation or the short one...)
<juri_>
the short one, because i don't have one of those on hand.
<lofty>
They're applicable to the stratix v too, I think
<juri_>
then i am all ears.
<lofty>
There are two big reasons and a few smaller ones
<lofty>
One is to do with the timing information, one is to do with how LABs are laid out
<lofty>
Take your pick :p
<lofty>
juri_: ^
<juri_>
so, you're going to have torture with a max-length design for the timing, or... ? :)
<lofty>
Do you know what the SPICE simulator is?
<juri_>
just barely.
<juri_>
i've installed it (used to sysadmin at an engineering college)
<juri_>
but as i was a sysadmin, and not a student.. grumble, grumble, destroycapitalism...
<lofty>
So, in normal, reasonable FPGAs, timing information is expressed as some inherent delay, plus a factor to express fanout delay
<lofty>
iCE40 doesn't even have the latter
<lofty>
But that would be reasonable, and this is an Intel/Altera FPGA, so instead timing information is expressed as a SPICE circuit and you need to propagate a waveform through all the elements in order to get your delays
<lofty>
Now, this is a pain, and so I have approximated the figures during routing, but that approximation leads to strange and weird behaviours like targeting a specific frequency, the router assuming it has met that frequency, and then final signoff timings says it failed
<lofty>
Or sometimes the opposite
<lofty>
(yes, this is what quartus_sta does)
<juri_>
ok, that's super weird sounding, but also probably more accurate.
<lofty>
It probably is more accurate, yes
<lofty>
The other problem is that Altera are...far more confident in their tooling than we are, and so have designed the LABs accordingly
<lofty>
A Cyclone V LAB has 10 8-input ALMs, plus 4 LAB-wide control signals for things like enables and resets.
<lofty>
To feed all of this, there are 46 tile-dispatch muxes to source signals from global routing
<lofty>
... You may notice the math doesn't quite add up here :p
<juri_>
super fun. :)
<juri_>
ok, i'll keep trying to acquire a reasonably priced (== my wife will not take my head highlander style) cyclone V.
<lofty>
Well, the two boards we use for testing are the Terasic DE10-Nano, and the Analogue Pocket
<lofty>
(why Analogue chose to send me a developer pocket I do not know, but I will not complain)
<juri_>
good to know. I ended up with a DE0-nano. soooo close. :)