whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
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<Guest59> From the documentation, yosys is able to "Conversion of full-featured Verilog to simple Verilog". How can i do this? In particular i am interested in only unrolling generate loops.
<Guest59> i've tried read_verilog in.v; hierarchy -top top; proc; write_verilog out.v
<Guest59> But the output is too different from the input.
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<whitequark[cis]> "only unrolling generate loops" isn't a feature yosys is offering
<whitequark[cis]> what that documentation line means is that yosys can convert arbitrary verilog to "structural verilog"
<whitequark[cis]> unfortunately "structural verilog" isn't any more well-defined than "simple verilog", so it's just confusing all around
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<Guest59> the fact that yosys produces structural-verilog answers my question, thanks
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<whitequark[cis]> perhaps that doc should be amended then
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