shoragan has quit [Read error: Connection reset by peer]
shoragan has joined #yosys
lexano has quit [Ping timeout: 268 seconds]
shoragan has quit [Quit: quit]
shoragan has joined #yosys
kristianpaul has quit [Ping timeout: 264 seconds]
citypw has joined #yosys
citypw has quit [Ping timeout: 260 seconds]
<lethalbit>
ya know, like, nya~
emeb_mac has quit [Quit: Leaving.]
citypw has joined #yosys
citypw has quit [Remote host closed the connection]
citypw has joined #yosys
citypw has quit [Ping timeout: 260 seconds]
lexano has joined #yosys
emeb_mac has joined #yosys
xutaxkamay has joined #yosys
<xutaxkamay>
hi, quick question, is there a way for yosys to ignore warnings about logic loops? i'm using a feedback loop for an asynchronous design, for now i'm just ignoring the check pass, but i'm not sure that's very wise
<xutaxkamay>
the reason of why i want to ignore the check and share pass is that it takes more probably than a week for it to finish
<xutaxkamay>
the synthesis works fine when there's a clock detected though
<lofty>
xutaxkamay: logic loops are undefined behaviour inside the Yosys IR - RTLIL
<lofty>
can you rewrite your feedback loop as a latch?
<jix_>
you can also manually break the loops by inserting a black box "buffer" module, then run synthesis, and finally map those loop breaking black boxes to a direct connection
<xutaxkamay>
lofty: i'm a bit a newbie in the hdl world, but the feedback loop is essentially here to maintain on purpose an infinite loop on a FSM where i can handle some handshake system with i/o ports to manage memory
<lofty>
that sounds like you could use a latch.
<xutaxkamay>
lofty: do you mind explaining what you have in mind? i know what a latch is but i'm not really seeing what you want me to do with it exactly
<lofty>
well, you're using it to maintain an FSM state, right? that's memory
<lofty>
a latch is a unit of memory, so trigger the latch as necessary
<xutaxkamay>
(i'm using vhdl) i use a signal to maintain the FSM state and use it inside the process sensitive list, which exactly causes the feedback loop yeah, so you mean just to add an enable input ?
<lofty>
unfortunately I'm not familiar with VHDL, but yosys provides a cell called `$dlatch` which is a literal latch
<xutaxkamay>
do you mind showing me a simple example in verilog that would translate to that dlatch? sorry for wasting your time
<lofty>
you can just use it like a module
<lofty>
but, uh
<lofty>
xutaxkamay: `yosys -p 'help $dlatch+'`
<lofty>
that is literally what the $dlatch cell is
<xutaxkamay>
yeah it has en enable input i see
<xutaxkamay>
but
<xutaxkamay>
i don't know how to say it but then isn't that basically requiring a clock?
<lofty>
no, because it's a latch and not a flop
<xutaxkamay>
okay but then enable needs to be oscillating between 0 and 1 in that case to keep triggering the latch
<xutaxkamay>
or im wrong ?
<lofty>
you will have some condition to hold state, right? in this case, the handshake with memory
<lofty>
(I will point out that writing asynchronous logic with the open tooling is a very bad idea, but I can't stop you)
<xutaxkamay>
lofty: so yeah you want me to use the input ports inside sensitive list and use them like i would do for a latch, but the problem is that i also need the inputs to know the state of another component (especially when a boolean input is false), i admit it it was probably a bad idea to start with, but i wanted to try it anyway
<xutaxkamay>
i've been looking to other languages like LARD but they don't provide sources anymore or even binaries
<xutaxkamay>
but yeah for sure, making it with a clock will prob make my life much easier
cr1901 has quit [Read error: Connection reset by peer]