whitequark changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/ | Bridged to #yosys:matrix.org
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
notgull has quit [Ping timeout: 260 seconds]
derekn has quit [Ping timeout: 252 seconds]
derekn has joined #yosys
emeb_mac has quit [Quit: Leaving.]
FabM has joined #yosys
FabM has joined #yosys
derekn has quit [Ping timeout: 264 seconds]
ikskuh has quit [Quit: Und tschüss!]
twix has quit [Quit: ZNC 1.8.2+deb3.1 - https://znc.in]
twix has joined #yosys
agg has quit [Remote host closed the connection]
agg has joined #yosys
derekn has joined #yosys
ikskuh has joined #yosys
pbsds has quit [Quit: The Lounge - https://thelounge.chat]
pbsds has joined #yosys
markov_twain has joined #yosys
emeb_mac has joined #yosys
schaeg has joined #yosys
schaeg has quit [Ping timeout: 240 seconds]
mewt has quit [Read error: Connection reset by peer]
mewt has joined #yosys
<Zevv> What's the typical procedure to optimize my design for size, what's an efficient method of finding out where the luts are being used?
<lofty> Zevv: a good place to start is to use `-noflatten` to synthesise the logic hierarchically, which tells you which modules are contributing the most logic
<Zevv> thanks, lemme check that
<Zevv> right, that's nice
<Zevv> good. good. Is there a proper place on IRC to ask generic verilog questions? I'm past the total noob level I guess, but still have a lot to learn.
<lofty> Zevv: #fpga?
<lofty> sorry, ##fpga
<Zevv> right, thanks. I checked #fpga but it was pretty empty
notgull has joined #yosys
FabM has quit [Ping timeout: 256 seconds]
Zevv has left #yosys [#yosys]
notgull has quit [Ping timeout: 260 seconds]
vancz_ has quit []
vancz has joined #yosys
nonchip has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
nonchip has joined #yosys