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<Zevv>
What's the typical procedure to optimize my design for size, what's an efficient method of finding out where the luts are being used?
<lofty>
Zevv: a good place to start is to use `-noflatten` to synthesise the logic hierarchically, which tells you which modules are contributing the most logic
<Zevv>
thanks, lemme check that
<Zevv>
right, that's nice
<Zevv>
good. good. Is there a proper place on IRC to ask generic verilog questions? I'm past the total noob level I guess, but still have a lot to learn.
<lofty>
Zevv: #fpga?
<lofty>
sorry, ##fpga
<Zevv>
right, thanks. I checked #fpga but it was pretty empty