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e_ter is now known as eater
11:03
<
Zevv >
On ICE40 I need to instantiate my bram explicitly using SB_RAM256X16 because I need the write mask bits, but now I don't know how to initialize the memory; how can this be done?
11:04
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11:04
<
xiretza[cis] >
can't yosys infer write masks nowadays?
11:05
<
Zevv >
oh, maybe; I'm not sure where I can find info about that?
11:05
<
tpb >
Title: 10. Memory mapping (at yosyshq.readthedocs.io)
11:05
<
tpb >
Title: 10. Memory mapping (at yosyshq.readthedocs.io)
11:05
<
Zevv >
sweet, thank you!
11:06
<
Zevv >
what's the general way inference works - like, how is my code matched against a potential infered implementation?
11:06
<
xiretza[cis] >
a big bag of heuristics
11:07
<
Zevv >
yeah that's what I expected
11:09
<
xiretza[cis] >
usually it works quite well, sometimes you have to do things like shift around read/write blocks to get transparency semantics that are possible in hardware
13:18
<
Zevv >
yes, found and read that, and got it working. thank you
13:18
<
Zevv >
I just passed the riscv compliance test
13:18
<
xiretza[cis] >
congrats!
13:19
<
Zevv >
one small step for mankind, one giant leap for Zevv
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13:24
<
lofty >
Zevv: what extensions do you plan to implement?
13:25
<
Zevv >
none, it's ment merely for control stuff that I'm too lazy to write logic for
13:25
<
Zevv >
I want it lean and mean.
13:25
<
Zevv >
problem with M is that apart from the mul it also needs to impl a div. That's kind of crappy
13:25
<
Zevv >
for F i'm not interested.
13:26
<
Zevv >
and csrr is not relevant for me as well, I won't be running linux on it ;)
13:26
<
lofty >
Zevv: Zmmul :p
13:27
<
Zevv >
it's now 30% of a UP5k, running at 40Mhz, including BRAM, SPRAM, UART and LED PWM.
13:27
<
Zevv >
good enough for now.
13:27
<
Zevv >
hey zmmul, nice
13:28
<
Zevv >
that's just a toolchain thing I guess, so it will assume mul is there but never emit a div
13:28
<
lofty >
And even having multiply accelerates division in practice
13:28
<
Zevv >
sure. but still. the sheer amount of work to get that going and test it and all
13:29
<
lofty >
Though I guess it depends if you're using a UP5K DSP or not
13:29
<
Zevv >
I might put MUL in though; I used 2 of my MAC_16s for the alu add and sub, so there's enough left
13:30
<
Zevv >
I guess it won't infer a 32x32 mul for me :)
13:30
<
lofty >
Sure it can
13:31
<
lofty >
Yosys has a script - mul2dsp - to convert large multiplications into chunks of small multiplications
13:32
<
lofty >
So yes, it can.
13:32
<
Zevv >
wow. lemme try that
13:32
<
lofty >
Are you passing -dsp to synth_ice40?
13:34
<
Zevv >
I just got MUL running
13:34
<
Zevv >
I'll have to throw out my manual MAC_16 stuff as well now
13:35
<
Zevv >
well, at least I learned something from implementing those.
13:39
<
Zevv >
well you got me there. I now do rv32im
13:39
<
Zevv >
let me upgrady my test suite
14:06
<
Zevv >
oh there's also E, didn't know that
14:06
<
Zevv >
well, actually, I don't care, it's just bram.
14:11
<
Zevv >
wait but -dsp does not infer my regular `+` and `-` to a MAC_16, how is that
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21:12
<
tnt >
Just rebuilt yosys/nextpnr for new laptop ... trying to build a project from a year ago and ...
21:12
<
tnt >
"Visited AIG node more than once; this could be a combinatorial loop that has not been broken"
21:14
<
tnt >
And `-noabc9` to the rescue.
21:16
<
lofty >
tnt: file a bug
21:16
<
tnt >
I'm checking with the last oss-cad-suite ATM to see if it's reproducible on a "known good build" of yosys
21:18
<
tnt >
and it does :/
21:19
<
lofty >
I mean, there's a non-zero chance that your design does actually have a combinational loop in it somehow
21:20
<
tnt >
That nextpnr somehow misses ?
21:21
<
lofty >
well, nextpnr doesn't get the netlist that ABC9 does. but anyway, I can take a look.
21:22
<
tnt >
Trying to package a test case rn.
21:48
<
lofty >
well, bugpoint is churning away on it.
21:50
<
tnt >
It's the async set in uart_tx.v on line 58.
21:50
<
tnt >
changing `always @(posedge clk or posedge rst)` to `always @(posedge clk)` makes it build.
21:50
<
lofty >
...then yes, you absolutely have a combinational loop, but one that nextpnr does not recognise
21:51
<
lofty >
now, ABC9
*should* catch this somewhere in the loop-checking code
21:52
<
tnt >
Also uart_tx.v is instanced twice ... and only one of the instance have the issue ...
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