ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<FL4SHK> okay so this bug appears to be in sv2v
<tnt> is it ? What's wrong with the verilog ? It looked fine to me.
<FL4SHK> the problem is the order in which task arguments are called
<FL4SHK> I had used named (.name(...)) arguments in the SV
<FL4SHK> and the order wasn't right in the final Verilog
<tnt> Oooohhhhh yeah, I completely missed that when reading the verilog.
<FL4SHK> I just found it
<FL4SHK> this explains everything
<FL4SHK> hm
<FL4SHK> it appears that there is still an issue with yosys
<FL4SHK> because even with not using named arguments
<FL4SHK> it still assigns 'x
<FL4SHK> without rst there's no issue
<FL4SHK> but with rst there is
<FL4SHK> or hm?
<FL4SHK> maybe with rst there's still a bug
<FL4SHK> I could have sworn I had put these in the right order
<FL4SHK> tnt: so yeah it still doesn't work
<tnt> :(
<FL4SHK> tnt: it might only be a problem with Verilog output
<FL4SHK> Is there a different way to output a netlist besides write_verilog?
<jix_> didn't read all the backlog yet, so might be missing context, but write_rtlil writes a netlist in yosys's native format
<FL4SHK> jix_: that sounds like something for me to try
<lofty> FL4SHK: there's also write_json
<FL4SHK> lofty: I'll give that a try
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<FL4SHK> what does "cells not processed" mean?
<FL4SHK> it looks like even the other output types have task input ports driven with 'x
<FL4SHK> I'm running yosys-nightly
<FL4SHK> so I'll try another version
<FL4SHK> appears to be a problem even with the Arch Linux yosys repo
<FL4SHK> yosys version*
<jix_> FL4SHK: it's set by the frontend and should be cleared by the hierarchy pass and AFAIK is basically just a marker that hierarchy still has to process stuff
<FL4SHK> jix_: I see
<FL4SHK> do I need another pass besides `read_verilog` and `proc`?
<jix_> you should run `hierarchy` between those
<FL4SHK> gotcha
<FL4SHK> that explains the issue I was finding
<jix_> the list of passes in `help synth` or alternatively `help prep` are complete examples of pass orders, and taking those (or a prefix) of them is usually a good starting point if you want to do something custom
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<FL4SHK> it looks like <= doesn't work
<FL4SHK> but = does
<FL4SHK> in a task
<FL4SHK> oh wait no
<FL4SHK> oh huh no it is <= that doesn't work
<FL4SHK> I'm satisfied with this result
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