peepsalot has quit [Quit: Connection reset by peep]
peepsalot has joined #yosys
bjonnh[m] has quit [Server closed connection]
peepsalot has quit [Quit: Connection reset by peep]
peepsalot has joined #yosys
bjork1intosh has joined #yosys
bjorkint0sh has quit [Ping timeout: 240 seconds]
so-offish has quit [Ping timeout: 246 seconds]
srk has quit [Remote host closed the connection]
srk has joined #yosys
FabM has joined #yosys
FabM has joined #yosys
FabM has quit [Changing host]
krispaul has joined #yosys
kristianpaul has quit [Ping timeout: 264 seconds]
jevinskie[m] has quit [Server closed connection]
jevinskie[m] has joined #yosys
Guest35 has joined #yosys
<Guest35>
Hello! I'm trying to do a logic synthesis with yosys, but I don't understand how to make sdc. Examples don't have something which look like Genus "create_clock [get_ports "$CLK_PORT"] -name "$CLK_NAME" -period 40 -waveform {0 20}". How to check my frequency in project? I'm sorry if this channel is not for asking questions like mine, but I really
<Guest35>
want to understang how works Yosys for my university project. Thank you :]