ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<Sarayan> zipCPU: the cycloneV ddr handling is a combination of a HMC (hard memory controller), some delay lines, dynamic termination control, pll and who knows what else. Plus code on a cpu (either hps or nios2) to calibrate the stuff. I suspect the general principles are fpga-independant, and the code half-independant too
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<ZipCPU> The problem is that the "hard memory controller" is not fpga-independent. Every FPGA has their own implementation of it. That makes it hard to port something from one device to another.
<ZipCPU> Worse, many FPGAs don't document the hard part of their memory controller.
<Sarayan> sure, but otoh half the calibration code is probably fpga-independant
<Sarayan> and what is needed/the concepts are similarly transverse
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