ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<marex> Hi, looking at https://github.com/YosysHQ/yosys/tree/master/techlibs/intel , do I understand it right that yosys is now able to assemble a bitstream for altera pre-alm FPGAs ? :O
<marex> entirely without quartus ?
<whitequark> no
<whitequark> it only did synthesis and it kind of doesn't anymore, that techlib is very old and I think untested
<marex> whitequark: oh, so, where do I find out which FPGAs are actually fully supported, so I know what to buy and what to avoid ?
<marex> the ice40 is obvious, maybe the gatemate is also OK ? but what else ?
<mwk> it's.... actually tested, with a big red QA FAIL stamped on it
<whitequark> ice40, ecp5
<marex> ah right, ecp5 too
<whitequark> gowin, I think?
<marex> I recall seeing something for that too
<marex> I got confused by the altera stuff, since I think rqou worked on it https://github.com/ArcaneNibble/project-chibi here
<whitequark> nexus if you can find those
<marex> and it seems the evil/ subdir would indicate that err ... well, it might be possible to read out the FPGA topologies from quartus data files, just by parsing those
<marex> I'm not quite sure how that is license-wise, it might be dubious
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<marex> whitequark: can I somehow grep the sources to find out what is supported now ?
<whitequark> you can look at nextpnr's README
<whitequark> since nextpnr is what actually makes the bitstream
<marex> ahhh, that is what I was looking for, thanks !
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<jn> Hi, i have a question about prjtrellis and MachXO2: what's a "row span"? (as seen in https://github.com/YosysHQ/prjtrellis/blob/master/tools/gen_globals.py#L23)
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