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<cr1901>
If I have a design with a clock enable, is there a way to get nextpnr to tell me "minimum period of the clock enable signal to propogate throughout the design"?
<cr1901>
Idea being "I want to embed the design in a clock domain faster than "Fmax when clock enable isn't used""
<tnt>
Nope
<tnt>
But you can probaby just deduce that yourself from the fmax of your design.
<cr1901>
Well, "Fmax of the entire design when the sub-design has its clock enable signal used" divided by "number of cycles clock enable inactive + 1" is certainly an upper bound to "Fmax of the subdesign when ce is used"
<tnt>
But even if you knew that number, there is no support for multi-cycle constrainst in current nextpnr.
<tnt>
I know there was some discussions I've seen on github, but ATM AFAIK nothing in mainline.
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<cr1901>
What's a multi-cycle constraint, specifically? Is it "the term for the scenario I just described", or something more specific?
<tnt>
It's when you tell the tools that some paths should be constrained to a multiple of the period. This is what is typically used to describe that you have a CE and it's only active once every N cycles.