16:15 <jangray> Greetings yosys community. I am exploring using yosys to techmap to a new FPGA I am developing called S3GA. See slightly stale blog at https://fpga.org/2022/11/30/s3ga-part-1-beginnings/. I'm enjoying learning how yosys does tech mapping. Yesterday I figured out how to use dfflegalize and an ff_map.v to techmap various device FFs that are

16:15 <jangray> initialized, optional sync reset/set, optional clock enable, etc. which map to various FD, FDE, FDR, FDS, FDRE, FDSE flop primitives, and sometimes some LUT+FFs (e.g. a flop initialized to 1, with sync reset to 0, clock enabled). Nice!

16:15 <tpb> Title: S3GA: A Simple Scalable Serial FPGA: Part 1: Beginnings | FPGA CPU News (at fpga.org)

16:20 <jangray> I'm about to start on place-and-route. The S3GA target is unusual / experimental in that it is a serial CLB, serial interconnect FPGA, partitioned into K=4 subclusters, recursively, with a FAT tree interconnect. The serial-ness aims to reduce the wiring and mux overhead of the interconnect; the  FAT tree interconnect topology aims to make it

16:20 <jangray> straightforward to route -- feed the design netlist hypergraph to KaHyPar and have it recursively min cost cut the hypergraph into K=4 partitions, subpartitions, etc.

16:26 <jangray> So P&R has various subproblems like partitioning the design down to LBs (logic blocks) of M=4 or M=8 LUTs, packing LUTs with their associated FFs when appropriate, picking which LUTs to evaluate on which cycles, and so forth. For the LUT+FF packing, I tried using yosys' extract command to (post-synth_s3ga) extract and pattern match LUT4=>FD into a

16:26 <jangray> beefier primitive, for example:

16:26 <jangray> / excerpt from s3ga/extract_lutff.v:

16:26 <jangray> module LUT4_FD #(parameter [15:0] INIT = 0) (input CLK, input I0, input I1, input I2, input I3, output Q);

16:26 <jangray>   wire D;

16:26 <jangray>   LUT4 #(.INIT(INIT)) lut(.O(D), .I0(I0), .I1(I1), .I2(I2), .I3(I3));

16:26 <jangray>   FD fd(.CLK(CLK), .D(D), .Q(Q));

16:26 <jangray> endmodule

16:33 <jangray> But when presented with a netlist with e.g. a LUT4 #(.INIT('b0110))=>FD extract fails because the INIT parameter doesn't match; extract -ignore_parameters does match the needle to the haystack, and replaces it with a LUT4_FD as desired, but the LUT4's INIT parameter is discarded. Is there a trick to have the haystack's elements' parameters (here

16:33 <jangray> INIT!=0) pattern match and reverse-project so that the substituted LUT4_FD's INIT parameter becomes that of the original LUT4 .INIT? I assume this is not possible in the current extract, and should proceed with explicit coding my post-synthesis netlist canonicalizations in C++ instead. Thanks for any comments / advice.

16:58 <jix_> jangray: not really familiar with extract, but AFAICT if you use constant inputs instead of parameters it could work ... and you can use techmap to translate between constant inputs and parameters (in both directions) so that might be a workaround

17:00 <jix_> oh and it might need -constports on extract which says it can be much slower, so maybe not the best approach